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Using PLLs for resonant tank control

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Dago

Wed Oct 14 2015, 01:57PM

Registered Member #538 Joined: Sun Feb 18 2007, 08:33PM
Location: Finland
Posts: 181

I made an ADPLL implementation in VHDL based on the phase-detector Wolfram had found and detailed in the OP:

I have included ModelSim project files, waveform setup scripts and simple test benches for the components.

The ADPLL consists of the phase-detector, a time-to-digital converter (essentially a counter that gives off a signed value of the phase difference between signal and reference), a filter (very simple first order RC-filter with bit shifts) and a phase accumulator as the oscillator. Unfortunately the ADPLL does not quite work yet, with the attached test bench it is stable for a while before it starts to oscillate:

I tried playing around with the filter parameters but didn't manage to get it stable yet. I calculated the parameters based on the paper I linked in an earlier post but it was not stable with those parameters either. I have a feeling there is some bug/fundamental problem with it that I am not yet seeing :)

I have a fancier second order IIR filter implemented with fixed point arithmetics but I am not quite sure how to properly calculate the coefficients.

One fundamental question: Should the filter behave as if the input value is a current or a voltage? Ie. if I set a fixed input value should the output value approach it linearly or logarithmically? The filter outlined in the paper approaches it linearly and my IIR implementation logarithmically.

Dago

Sun Oct 18 2015, 01:24PM

Registered Member #538 Joined: Sun Feb 18 2007, 08:33PM
Location: Finland
Posts: 181

I managed to get my VHDL-implementation working. I have uploaded all of my VHDL to GitHub:

parasole

Tue Nov 24 2015, 08:56AM

Registered Member #54647 Joined: Wed Mar 18 2015, 02:52PM
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Posts: 13

Interesting topic, then I broaden my search and found that there is ADPLL IC available from TI: 74ls297
If you do a search for this IC than you will get quite a number of interesting results and one being VHDL implementation of this IC...

Wolfram

Sun Dec 20 2015, 10:44PM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

I forgot to update this thread with actual test results. I implemented this phase detector in my heater prototype, and I've verified that it works as well as expected. Initially I had some trouble getting a stable phase lock, but this turned out to be caused by problems in my primary current phase measurement circuit. My circuit had the CT loaded by diodes, and their significant and non-linear capacitance introduced current-dependant phase shifts and duty cycle variations that resulted in erratic behavior. Once I fixed the current phase sensing, the circuit started working correctly. It acquires lock at very low DC bus voltages, and it maintains lock through the whole mains period with unsmoothed rectified mains on the DC bus.

I attempted to adjust the switching phase angle by injecting a DC current into the loop filter capacitor node, but I never got this to work right. Instead, I implemented switching phase control by adding a delay circuit between the VCO output and the phase detector input. By adjusting this delay, I can adjust how early or late the IGBTs will switch in relation to current zero crossing.

Uspring: The idea with updating the flip-flop on both clock edges is brilliant! Especially as you suggest for TCs and other applications with rapid phase changes. It takes some more logic to implement, but this is no problem if it is done in an FPGA.

Dago: Nice implementation! This will save me some work when I migrate my project to an FPGA some time in the future.

parasole

Mon Dec 21 2015, 07:51PM

Registered Member #54647 Joined: Wed Mar 18 2015, 02:52PM
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I did some play around Dago code (thanks for it!) and came up with lighter version which could be used with additional controller (cheap AVR) for service functions. The core part came up with only 331 LE which is fitting nicely in cheap CPLD device (EPM570 in my example). Another microcontroller could be used for temperature control (the function which I excluded from CPLD since it requires lot of resources), PDM modulation level setting (rotary encoder as input to the controller) as well as different measurements like currents, working frequency and so one.

parasole

Mon Jan 11 2016, 05:10PM

Registered Member #54647 Joined: Wed Mar 18 2015, 02:52PM
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Posts: 13

Further exploring ADPLL topic, I found interesting paper with an alternative solution for ADPLL, the idea is to change the tracking step, with narrow one and precise while in sync and widening when sync is acquired...
I did implement M_change module as I understood it, it looks to be working in the sim, however not fully sure about how well it is done. Any one more proficient in vhdl and want to have a look let me know about...
]fpga-based_induction_heating_adpll.pdf[/file]

Sigurthr

Mon Jan 11 2016, 05:46PM

Registered Member #4463 Joined: Wed Apr 18 2012, 08:08AM
Location: MI's Upper Peninsula
Posts: 597

Wolfram wrote ...

Uspring: The idea with updating the flip-flop on both clock edges is brilliant! Especially as you suggest for TCs and other applications with rapid phase changes. It takes some more logic to implement, but this is no problem if it is done in an FPGA.

I'm just now seeing this thread, excellent work Wolfram et al. I've commented on the shortcomings of the 4046 in SSTC applications a lot over the years but never had any solution or hard data on what causes the problems. Thank you for clearing both up! Out of six PLL coils I only ever got one to work right, and I've damned near framed the driver, haha.

Any chance at a schematic for this modified solution for TC use? I'd love to try implementing this fix in the future. Any application notes you can add would be appreciated, especially since you had to revise your tank sense circuitry.

Uspring

Wed Jan 13 2016, 02:19PM

Registered Member #3988 Joined: Thu Jul 07 2011, 03:25PM
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Posts: 711

Sigurthr wrote:

Any chance at a schematic for this modified solution for TC use?

You need 2 copies of Wolframs circuit:

In the first circuit, you input VCO_F and I_TANK and in the other one the inverted versions of these signals. You the average the outputs, e.g. by connecting the second circuits Q with an extra R3 to C1.

Wolfram

Wed Jan 13 2016, 03:58PM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

Uspring wrote ...

Sigurthr wrote:

Any chance at a schematic for this modified solution for TC use?

You need 2 copies of Wolframs circuit:

It is possible to simplify the circuit a bit further without changing its operation. An XOR with the inputs inverted is identical to a regular XOR, so you don't have to duplicate this part. This also saves an inverter, since you only need to invert the reference phase input for the second phase detector.

This solution might not be as fast as it could be, whenever one flip flop is updated with the latest sampled value, the other one will still be driving the loop filter with the previous sampled value. I guess this is gives it a pole in the Z plane.

This can be solved with just a tiny bit more logic. Decomposing the XOR function into two separate gates allows us to enable each D-FF only on its the half-cycle that it sampled. In both these circuits, the 74LVC1G14 can be replaced by a 74LVC1G57 if you want to minimize the number of different chips in the design. The logic can of course also be implemented in any technology where the neccessary logic is available. Also note that these double-edge phase detector designs are untested as of now.

The speed advantage over the single edge phase detector is only worth the added complexity in cases where where the phase can change significantly from one half cycle to the next. A typical case is in a DRSSTC. I don't know if the dual-edge loop filter has an advantage over the single-edge one in a typical SSTC. In an induction heater the benefit is insignificant, wo I will be sticking to the single-edge one for now.

Lastly, I've attached a schematic of the PLL/PDM core in the latest revision of my induction heater. This shows another implementation of the single-edge resonant phase detector, using the XOR PD in the 4046. Here you can see the improved current sign detector and the fully synchronous enable logic as well.

Uspring

Thu Jan 14 2016, 11:00AM

Registered Member #3988 Joined: Thu Jul 07 2011, 03:25PM
Location:
Posts: 711

This solution might not be as fast as it could be, whenever one flip flop is updated with the latest sampled value, the other one will still be driving the loop filter with the previous sampled value.

Yes, a nice circuit modification. For fastest response one also needs to take into account, that a simple RC low pass filter involves long term memory of previous phases. That can be seen by its representation as a convolution integral in the time domain. Better filters seem possible. For optimisation freaks an endless topic

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