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Registered Member #989
Joined: Sat Sept 08 2007, 02:15AM
Location: São Paulo, Brazil
Posts: 476
Hi all, I received today the datasheet of one of my Sharp LCD's here, and I noticed that the interface of that LCD is LVDS... And on the datasheet it reffers to a IC that encodes the computer RGB/Sync data to LVDS data... The IC is DS90C363
I will control the LCD with my FPGA Dev board, and the FPGA does support LVDS input/outputs, but I never used them. I see that enter 6 wires ( R G B H V ) and output 3 pairs (each pair correspond to one signal in LVDS), so how it encodes 6 signals into 3 LVDS signals? Normal 2-to-1 digital encoder or something else? Its easy to simulate on FPGA this, but I didnt understand what is uses for enconding =/
Registered Member #2099
Joined: Wed Apr 29 2009, 12:22AM
Location: Los Altos, California
Posts: 1714
I won't say RTFDS. The pair of parts forms what's called a SERDES = Serializer-Deserializer. The IC datasheet explains that each LVDS differential pair carries the data from seven TTL input pins, using an internally generated bit clock 7 times faster than the parallel I/O clock. The parallel I/O is actually 21 pins, so in standard application R, G, and B each get 6 wires for a digitally coded pixel intensity.
Since your FPGA supports LVDS, you might be able to bypass the LVDS serializer (transmitter) part. See if the FPGA has an internal PLL to do the clock frequency multiplication; otherwise you would need to clock it at 7 x your pixel rate (or buy the serializer & use more FPGA I/O pins).
If you are running more than 100 Mb/s per pair to your LCD panel, good physical routing of the wires is critical. But you can easily go many meters using controlled-impedance transmission lines and terminations.
Registered Member #989
Joined: Sat Sept 08 2007, 02:15AM
Location: São Paulo, Brazil
Posts: 476
Hmm, My FPGA doesnt have PLL but have DCM (that can multiply the clock too), I will make it for a few test for learning, my old LCD was MUCH wires (5bit for each color, + Hsync + Vsync + Dot clock, that is much wires arround, and 800x600 only) but I fried the backlight of it with a homebrew drive =X (I never will do this again), now I will start with my 1024x768 18bit Color panel, I dont know if I will use all the data band, (I think only three colors, so I can down the clock)
I have this kit: Its a cheap kit, but have much things that I can do, the oscillator onboard is 16Mhz, so I will multiply it much =P (that fpga supports virtually infinite clock, depending of the application, let ISE say what is the maximum I can run)
The thing that I didnt understand is how will I send the data to LVDS interfaces? As you say, it will be a 21-to-3 enconder with 7 times the enconding clock that the 21bit bus uses, is that correct?
Edit: As I see, the LVDS transmitter on FPGA is 7-to-1 LVDS Transmitter, so I think it may be easier than I think =P
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TTL Parallel to LVDS Converter
