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Odin The All-Fragger: a large DRSSTC

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Ash Small
Thu Jul 10 2014, 09:47PM
Ash Small Registered Member #3414 Joined: Sun Nov 14 2010, 05:05PM
Location: UK
Posts: 4245
teravolt wrote ...

to bad a big series diode in the couldn't be added to each IGBT drain to block the reversal. do you think that it would help with hard switching

a big Schottky, maybe?

Instantaneous reverse recovery, and negligible forward voltage drop?

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Sigurthr
Thu Jul 10 2014, 11:52PM
Sigurthr Registered Member #4463 Joined: Wed Apr 18 2012, 08:08AM
Location: MI's Upper Peninsula
Posts: 597
Blocking the body diode with series and antiparallel schottkys is what I've been doing on my SSTC bridges. I've been wondering how it would perform in a DRSSTC environment. I haven't seen it used on DR coils yet.
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Steve Conner
Fri Jul 11 2014, 10:09AM
Steve Conner Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Unlike MOSFETs, IGBTs don't have parasitic body diodes. They have a parasitic zener-transistor-junction thing that breaks down at about 10V.

So when you see an IGBT with a diode built in, the diode is actually a proper fast and soft recovery diode on a separate chip, wire bonded in parallel with the IGBT die. There would be no point in "blocking" it unless you wanted to upgrade an old diode to a newer generation.

One thing *I* haven't seen is the Class-DE snubber capacitors used on a DRSSTC bridge. Well, Steve and Eric probably used them in phase shift controlled QCWs, but I wonder if they would help a lower frequency coil with IGBT bricks.

By a quick back-of-the-envelope calculation, a 50nF snubber capacitor would cut the switching losses of a 300 amp IGBT brick in half when it was operating in the phase lead mode and hard switching 300 amps of inductive current. This is just a rough figure, the actual value depends on the fall time of the specific IGBT.

However, if there wasn't enough commutation current to charge the capacitor, the switching losses would get worse than if there were no capacitor. Basically it moves the point of lowest switching losses from ZCS, to some finite current, which is certainly an advantage in a phase shifted QCW.
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Goodchild
Fri Jul 11 2014, 02:15PM
Goodchild Registered Member #2292 Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795
If I'm not mistaken I asked Steve about his setup, he tried them but never got them working properly, rather he took the simpler approach of just hard switching on turn off and ZCS on turn on, simple and effective. This was a while ago however, I’m not sure if he ever went back to that approach.

I managed to get full ZCS working a little while back. It's an incredibly effective method of switching and allows turn-off anywhere there is enough current to commentate the voltage in the parallel capacitor. In some cases you don't even need external snubbers, most of the time the parasitic capacitance of the switch is enough to commutate the voltage. Usually external capacitance is added when there is not enough rise or fall time for the switch to transition. Even then usually only a couple nF has to be added to extend the rise and fall time to 100nS or more.

The two reasons I like it is that it allows you to do phase-sift modulation of the bridge current and also completely eliminates spikes/nasty transients. You get a lovely linear rise/fall time with a dV/dt of your choosing.

The last benefit is that EMI and harmonics from bridge transitions are heavily reduced, due to the rise and fall times being much sallower. In contrast to ZCS where they must be as close to square as possible.

The disadvantage however is complexity. Such a setup is tedious to setup and tune and requires a very complicated controller. I used an FPGA, and Steve I think used a Soc.
I think that for a normal DR the advantages don’t out way the added complexity. However in a QCW, this added control allows you to eliminate the class D modulator hardware, so the added complexity balances out in the end.
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Steve Conner
Fri Jul 11 2014, 03:18PM
Steve Conner Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Interesting info, thanks. I don't see how it adds much complexity to a normal DRSSTC, surely with a phase lead DRSSTC driver you can just add the snubber capacitors and turn the phase lead up a little more?

My PLL driver can be phase shift modulated by hooking a voltage in place of the target phase pot. I was wondering if this would be a good way of controlling a halfbridge Class-DE QCW.

With a halfbridge, you can't phase shift two bridge legs against each other, so phase shift modulation degenerates to either PWM or detuning. I'm proposing to do it by detuning upwards, so the current will be inductive and suitable for Class-DE commutation.
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Goodchild
Sat Jul 12 2014, 01:25AM
Goodchild Registered Member #2292 Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795
Steve Conner wrote ...

Interesting info, thanks. I don't see how it adds much complexity to a normal DRSSTC, surely with a phase lead DRSSTC driver you can just add the snubber capacitors and turn the phase lead up a little more?

My PLL driver can be phase shift modulated by hooking a voltage in place of the target phase pot. I was wondering if this would be a good way of controlling a halfbridge Class-DE QCW.

With a halfbridge, you can't phase shift two bridge legs against each other, so phase shift modulation degenerates to either PWM or detuning. I'm proposing to do it by detuning upwards, so the current will be inductive and suitable for Class-DE commutation.

I wish it was that easy, but phase lead is only the first part of the equation, you also need an extended dead-time between the high and low side switch transitions.

This dead time is = the rise + fall times. On most of the bridges I played with this amounted to about 250nS dead time, with a 400KHz Fres. For slower transistors (like bricks) this dead time will be even larger.

The problem is that this dead-time can't be introduces at the gates of the IGBTs because it would cause the IGBT to operate in the linear region for a large part of that dead time, it's also impractical to implement such a long RC when the gate C is so small.

So the only other option is to create it before the gate drive; for GDT drives this means 2 GDTs and added driver circuitry and delay circuit. Phase moderation adds even more circuitry on top of this setup.

I implemented every part except for the GDT drivers in an FPGA, this made all the parameters of the circuit, dead-time, phase lead, etc controllable and digitally tun-able.

I tried an analog version of this circuit before the FPGA, and although it works it was much more fussy and used a needless amount of analog cludgery.
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Steve Conner
Sat Jul 12 2014, 04:44PM
Steve Conner Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Oh, I think I have all that analog cludgery already. smile My PLL driver has a deadtime generator that inserts periods of 0V into the gate drive output, so it goes +12V, 0V, -12V, etc.

The 0V step seems to work OK when driving smaller devices directly, as it applies 0V to all of the gates. This doesn't turn them off as fast as a negative voltage would, though.

The outboard drivers translate both -12V and 0V into -12V, so the output from them is textbook stuff.
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Thomas W
Sat Jul 12 2014, 05:17PM
Thomas W Registered Member #3324 Joined: Sun Oct 17 2010, 06:57PM
Location:
Posts: 1276
Steve Conner wrote ...

Oh, I think I have all that analog cludgery already. smile My PLL driver has a deadtime generator that inserts periods of 0V into the gate drive output, so it goes +12V, 0V, -12V, etc.

The 0V step seems to work OK when driving smaller devices directly, as it applies 0V to all of the gates. This doesn't turn them off as fast as a negative voltage would, though.

The outboard drivers translate both -12V and 0V into -12V, so the output from them is textbook stuff.

Oh? i thought it went +24, 0v -12v?
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Steve Conner
Sat Jul 12 2014, 05:23PM
Steve Conner Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
The PLL driver board's own output is bipolar for driving GDTs. If you want a waveform to pass through a transformer, it has to be symmetrical (to be pedantic, the positive and negative areas must be equal) so when using a GDT the positive and negative gate voltages must also be equal.

The outboard drivers use a small GDT followed by a MOSFET stage, so they don't have this limitation. The MOSFET stage turns +12V input into +24V output, and 0 and -12 go to -12V output.
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Goodchild
Tue Jul 15 2014, 01:30AM
Goodchild Registered Member #2292 Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795
Hmm well the you may be good to give it a try, particularly if you already drive the gates individually via high side gate drive. I would say give it a go.

I have found that tuning the ZVS in spice gives a good ball part before trying it on the real thing.
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