Pulse skipping (aka freewheeling) mod for UD2.x drivers

Hydron, Wed Nov 16 2016, 07:56PM

There has been some discussion and interest in one of the UD3 features, namely the Freewheeling/Pulse skipping method for primary current limiting. (refer to and )

I though I'd have a quick go at sketching up a mod for a UD2.x driver to add the feature without going fully programmable like the PSoC based UD3.

This is initially done for Kizmo, who intends to give it a go and report back, but any criticism or suggestions are welcome.


Operation:
- first FF uses the asynchronous clear to latch the OCD event until the next switching transition, when it is cleared
(same as how the old circuit latches the OCD until the next interrupter pulse, but with startup state being set rather than cleared)
- second FF synchronises the freewheel signal to a switching transition edge
- third FF toggles every time freewheeling is activated (selecting which leg of the bridge to disable)
- together with the OR and AND gates, this means that when the OCD is tripped there is at least one full cycle when both IGBTs on one leg of the bridge are turned off
- the gate drive will always be disabled for a whole number of full cycles, avoiding DC offset in the GDTs
- the thermal load should be spread between both bridge legs due to the alternate selection of which leg to use for freewheeling current
- the PRE and CLR inputs of the flip-flops are connected in such a way that freewheeling is disabled at the start of each interrupter pulse (third FF is set to a defined initial power-up state by the RC on PRE, and toggles thereafter)

Notes:
- Might be a way to reduce the IC count, but haven't thought up a method yet (needs 2x 74HC74, 1x 74HC32, 1x 74HC08)
- If spreading the load evenly between the two half bridges is unnecessary then the third flip-flop and OR gates can be omitted, cutting the IC count by half. In this case diodes and a ~10k discharge resistor should be used to replace the OR gate on the left
- This circuit provides no pulse-length limit, and it is highly recommended to implement one or at least have an undervoltage lockout on the gate drive supply if there is any chance of the interrupter signal getting stuck on

Implementation:
If you have 2x UD2.7 available, then this mod can be added without any track cutting or modding of the driver:
UD2.7 #1:
- Wire up feedback CT as normal, skip OCD CT connection
- Pins 3 and 4 of the phase jumpers go to mod inputs labeled (1) and (2)
- Outputs labeled (4) and (5) go to phase jumper pins 1/2 or 5/6 (depending on phase required)
- Use JP1 to enable UVLO, and preferably also connect JP1 pin 1 from board #2 as well, so that both 24V supplies are monitored
UD2.7 #2:
- Connect OCD CT as normal, set limit as desired for pulse skipping
- Connect mod input labeled (3) to JP1 pin 2
- Outputs labeled (6) and (7) go to phase jumper pins 1/2 or 5/6 (depending on phase required)

Can be done with 1 driver with some track cutting:
- connect (1) and (2) as before
- cut the connection between the OCD output (LM311 + 1n/1k RC) and the CLR input of the OCD flip-flop (IC6A in UD2.7), leaving UVLO attached if present. The OCD output goes to (3)
- Each UCC driver will need to take separate inputs from (4)/(5) and (6)/(7), so a couple more tracks to cut and solder to

For other UD2.x versions adjust as required (suggest referring to UD2.7 schematic to work out what's going on!)

Also see the simulation capture below:
(ignore first skipped pulse at the start, caused by laziness not setting the flip-flop startup state properly)
Leg 1 enable: blue
Leg 2 enable: red
Primary current (limit set at 500A): green