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Registered Member #618
Joined: Sat Mar 31 2007, 04:15AM
Location: Us-Great Lakes
Posts: 628
Trying to layout a H-bridge PCB for SSTC/DRSSTC using to-247 Igbts, and an old CPU Heat sink, I have most of it set up but I'm having some concerns on trace to trace spacing especially if this was used for DRSSTC since there are higher currents and higher voltages present on the primary then with just a SSTC.
This would be used on smaller coils in the 2in-4in range, I was trying to find how close others had traces, but most are using the mini blocs (don't blame you) or are using bricks for bigger coils.
Registered Member #2481
Joined: Mon Nov 23 2009, 03:07PM
Location: ITALY
Posts: 134
A DRSSTC has higher currents but NOT higher voltages than a SSTC on the bridge. Voltage on the components/traces of the bridge is just the DC on the bus (+ spikes...)
Registered Member #1902
Joined: Fri Jan 02 2009, 07:59PM
Location: Lancaster, NY
Posts: 75
With the appropriate TVS diodes and snubber caps you should be okay. Another trick I would recommend if the traces are exposed copper you should lay a bead of solder to reduce resistance. Good luck!
Registered Member #15
Joined: Thu Feb 02 2006, 01:11PM
Location:
Posts: 3068
Corey wrote ...
With the appropriate TVS diodes and snubber caps you should be okay. Another trick I would recommend if the traces are exposed copper you should lay a bead of solder to reduce resistance. Good luck!
-Corey
Laying a bead of solder should have no effect whatsoever on the breakdown voltage between two adjacent traces, if thats indeed what your statement was pertaining to.
Also, important to mention that the IPC standard spacing guidelines i mentioned above are just that guidelines, and are quite conservative (derating built in). They account for both external arcing through air (the one equation i referenced was air at sea level), and creep across the surface of the board. It also assumes no conformal coating on bare copper traces or soldermask, so its a worst case.
Registered Member #618
Joined: Sat Mar 31 2007, 04:15AM
Location: Us-Great Lakes
Posts: 628
I noticed that EVR, and so I was trying to research possible coatings, with out getting some fancy stuff I was thinking of using colored polyurethane, to add a dieelctric strength and a touch of the professional look, but I can't find much info on heat tolerences for soldering purposes.
Registered Member #1902
Joined: Fri Jan 02 2009, 07:59PM
Location: Lancaster, NY
Posts: 75
EastVoltResearch wrote ...
Corey wrote ...
With the appropriate TVS diodes and snubber caps you should be okay. Another trick I would recommend if the traces are exposed copper you should lay a bead of solder to reduce resistance. Good luck!
-Corey
Laying a bead of solder should have no effect whatsoever on the breakdown voltage between two adjacent traces, if thats indeed what your statement was pertaining to.
Also, important to mention that the IPC standard spacing guidelines i mentioned above are just that guidelines, and are quite conservative (derating built in). They account for both external arcing through air (the one equation i referenced was air at sea level), and creep across the surface of the board. It also assumes no conformal coating on bare copper traces or soldermask, so its a worst case.
I was pertaining to the current levels experienced during drsstc primary ring up. I've used this technique to beef up leads on Mazilli driver boards to reduce resistive losses.
Registered Member #1334
Joined: Tue Feb 19 2008, 04:37PM
Location: Nr. London, UK
Posts: 615
You might find a calculator I wrote a few years back helpful on this - it implements the IPC 2221A rules in JavaScript - see - over 5000 hits a month at the moment... There is an implementation of the UL rule on track separation included.
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Trace spacing limits in DRSSTC/SSTC
