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PLL SSTC, how to set it up?

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raff

Sun Sept 27 2009, 01:55AM

Registered Member #2315 Joined: Tue Aug 25 2009, 02:35AM
Location: Leyte, PH
Posts: 161

Hi,

better late than never.. Im also in the path of making PLL SSTC... I have been looking at the datasheet but FAILED? to see the USE of R2.. all I could see in the graphs/typical center freq is uring R1 and C1 with R2 open...

what happens btw if R2 is left open?

Dr. Dark Current

Sun Nov 08 2009, 03:27PM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

A few more questions.. What happens if the capacitor on the output of the phase comparator is left open? Does it lock instantly or does it go mad?

If the phase tuning pot is disconnected, is the phase set to 0 degrees?

Steve Conner

Sun Nov 08 2009, 05:52PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

If you leave the loop filter capacitor out, it will go mad.

The last question isn't so easy to answer, because the phase that this circuit actually locks to is ill-defined. It's a Type 1 PLL, so the phase shift that it settles to will depend on how far the VCO frequency is from the design centre frequency. For my second driver, I changed to a Type 2.

Dr. Dark Current

Sun Nov 08 2009, 06:48PM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

Steve McConner wrote ...

The last question isn't so easy to answer, because the phase that this circuit actually locks to is ill-defined. It's a Type 1 PLL, so the phase shift that it settles to will depend on how far the VCO frequency is from the design centre frequency. For my second driver, I changed to a Type 2.

Well.. when I've been thinking about the circuit, this was the conclusion I came to as well! That the "phase" pot doesn't actually set phase, but something a bit different... So when the coil is supplied e.g. from half-wave rectified mains, the detuning of the coil acutally changes the phase too.

Do you have your second driver on your site?

Steve Conner

Sun Nov 08 2009, 07:00PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

You win a cookie, sir!

In formal control theory terms, the pot sets the setpoint for the phase control loop, but the loop doesn't have much loop gain, so it settles with a large error which depends on the VCO control voltage. Well, I say "depends", but it's worse than that. The loop has no loop gain, so the error actually *is* the VCO control voltage. By a similar argument you can see that the frequency and phase pots in my original circuit both do the same thing, so one of them can be left out, as many people have done.

I didn't see any of this at the time, and only understood it long after I'd built the circuit.

The second driver is on my DRSSTC page:

It's much more complicated because it was designed around a commercial contract that ended up falling through. So it has full protection circuitry, and so on.

But the main difference is that it has a Type 2 PLL, which just means one more integrator in the loop, giving a steady-state phase error of zero. You can achieve the same thing at lower complexity with the 4046's Type 2 phase detector, but I ran out of patience with that. You might have better luck.

Note that even a Type 2 PLL can have dynamic phase error. While the frequency is changing, the VCO will lag behind, as it takes the integrator some time to respond. In general the frequency will change, such as in the detuning example you gave. This is why I thought the Type 1 would be good enough at first.

Luca

Tue Nov 24 2009, 10:15AM

Registered Member #2481 Joined: Mon Nov 23 2009, 03:07PM
Location: ITALY
Posts: 134

Hi guys,
this is my first post on this nice forum

Iâ€™m trying to design a SSTC (self resonant) and I am considering the use of a PLL in the control circuitâ€¦

In particular, I would use the 74VHC4046 which seems to be very popular in such applicationâ€¦ Anyway, as some of you have pointed out, such PLL (comp type I) offers 90Â° of phase shift between the IN signal and the OUT of the VCO, when the input frequency is equal to the VCO center frequency (fo). Moreover, such phase shift changes from 0Â° when f=fmin to 180Â° when f=fmax.
The reason is that the phase error signal (PC out, pin 2) feeds directly the VCO input, which spans from 0 to Vdd.
As I have seen in some schematics (such the one in the first link of this topic), to overcome this problem usually a dc bias is added to the VCO input (pin 9) and such bias is tuned to minimize the phase shift.
However, I think that adding a dc bias to the VCO input simply changes the frequency at which there is 90Â° phase shift. I mean, if you tune the PLL to have zero phase shift at a certain frequency (fx), if then the resonance freq. of the coil changes from fx the phase shift will increase (you should tune the PLL again).
Another issue that I see is that if you add a dc bias to the VCO input you reduce the frequency range of the VCO, since the VCO spans from fmin to fmax with corresponding input voltages from 0 to Vdd. So, if you add for example Vdd/2 to the VCO input, the output freq. will never go below foâ€¦
Do you agree with me?

People that have realized SSTC based on such PLL have found instability of the phase shift while running the coil?

I was also thinking to use phase comp II type (which always gives 0Â° phase shift when lock) but I think that its noise immunity is too small, probably for this reason people who tried this comparator found some problems (instability)...

Thank you for your feedback!

Luca

Dr. Dark Current

Tue Nov 24 2009, 06:17PM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

Would it be as simple as switching the phase comparator type while leaving the rest of the circuit intact?

Dr. Dark Current

Sun Nov 29 2009, 07:12PM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

Dr. Kilovolt wrote ...

Would it be as simple as switching the phase comparator type while leaving the rest of the circuit intact?

Anyone thinks this could work? I don't see into the PLL circuit that much.

Steve Conner

Sun Nov 29 2009, 07:44PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

Well, as was mentioned in Iamsmooth's PLL thread, the PC2 comparator in the 4046 doesn't tolerate noise well. This is because it uses a digital state-machine triggered by the rising and falling edges of the signals, unlike PC1 which just takes the average of things.

I tried PC2 and could not get it to lock reliably, a Tesla coil being quite a noisy environment. Maybe I just made a mistake, but I gave up on it.

For my Mk2 driver, I just integrated the output of PC1 with an op-amp integrator. This resulted in a Type 2 loop, but with the noise immunity of PC1. See Iamsmooth's "Help with 4046" thread for more details.

Dr. Dark Current

Sun Nov 29 2009, 09:59PM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

Something like this?

How to select the values of R and C of the integrator?

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