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A 16 bit CPU implemented in 7400 series logic

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Bjørn

Sun Feb 12 2006, 09:50AM

Registered Member #27 Joined: Fri Feb 03 2006, 02:20AM
Location: Hyperborea
Posts: 2058

A high performance 16 bit RISC CPU
Harvard style architecture that executes all instructions in a single clock cycle.
8 registers, the program counter is mapped to register number 8.
Conditional execution of all instructions.
Condition flags are set on demand.
All instructions execute in a single clock cycle.
Branch-link instruction where the program counter is copied to R6.
Register bank with two read ports and one write port, all accessed during the same cycle.

Huge schematics
Emulator and assembler
Instruction Set

It is not optimized for size or speed. I have tried to route a dual layer PCB for it without any luck. There are about 130 chips in the schematics.

Tim Koene

Tue Feb 14 2006, 08:24AM

Registered Member #37 Joined: Sun Feb 05 2006, 05:35PM
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Posts: 13

Wow Bjoern,

Amazing work! I might soon have a way to make huge circuit boards. Perhaps you could split it into 4 smaller boards which *can* be routed? Just a suggestion.

Bjørn

Tue Feb 14 2006, 09:45AM

Registered Member #27 Joined: Fri Feb 03 2006, 02:20AM
Location: Hyperborea
Posts: 2058

Splitting it up might be a usable solution, maybe some sort of backplane where each functional unit is a card. That way instructions can be added or improved by just swapping cards.

...

Tue Feb 14 2006, 03:00PM

Registered Member #56 Joined: Thu Feb 09 2006, 05:02AM
Location: Southern Califorina, USA
Posts: 2445

wow, this reminds me of the magic-1 computer; I find it really amazing how a bunch of simple logic gates can be used to make an intelligent being... Heck, I can telnet into magic over the internet and play games on it!

Keep up the good work!

Hazmatt_(The Underdog)

Tue Feb 14 2006, 10:29PM

Registered Member #135 Joined: Sat Feb 11 2006, 12:06AM
Location: Anywhere is fine
Posts: 1735

looks cool!

also looks like another 8051, *waits for verbal abuse*

JimG

Wed Feb 15 2006, 08:07PM

Registered Member #52 Joined: Thu Feb 09 2006, 04:22AM
Location: Austin TX
Posts: 57

After designing a number of ALUs by hand in college I have become fascinated with implementations that others have done.

Have you simulated your CPU yet?

I was really impressed by the magic-1 computer when I first heard about it. I was a little let down to see that it used 74f381s to do its math operations, but it's understandable considering that the machine was already fairly complex for a wire wrapped computer.

Bjørn

Wed Feb 15 2006, 10:47PM

Registered Member #27 Joined: Fri Feb 03 2006, 02:20AM
Location: Hyperborea
Posts: 2058

Yes, it runs fine in a digital simulator. It has not ben run in a full simulation and I don't know of any programs that are capable of doing it in a simple way. It would not be very interesting since the design of the PCB would be the most important variable anyway.

When it comes to 8051 I have taken great care to avoid most Intel ideas.

Carbon_Rod

Thu Feb 16 2006, 03:03AM

Registered Member #65 Joined: Thu Feb 09 2006, 06:43AM
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Posts: 1155

Most people use VHDL and build fpga based systems etc.. for fun...
(small units with a loader can be well under $75.-)

I have some 8" Si wafer if you want to make your own chips :D

Protel says it can do this sort of thing, but I have never tried it with the proto-shops system. Also, multisim (now part of NI) can do VHDL (extra plugin) so it should be pretty easy to import or build a sim Block.

Synopsys can build/sim ASICs just fine, but it is hard to get terminal time with and is an insane price.

UMPS (Universal Microprocessor Simulator) was an old block design tool that could build and test core designs. It had a Academic trial too if you can find this old program. (a few meg)

I was going to have a look at this GPL VHDL project to see how well it would import into the other systems (let me know what you think if you get time to try it out):

The 8051 & 8052 VHDL free model is around too if you need an example.
check here:

Bjørn

Thu Feb 16 2006, 03:41AM

Registered Member #27 Joined: Fri Feb 03 2006, 02:20AM
Location: Hyperborea
Posts: 2058

The intended target actually is a FPGA, it is 16 bit so it will fit well with the RAM in a Spartan II. I found that VHDL takes away much of the fun so I tested it in a way that was painless and interesting.

The register bank will be mapped to a RAM block so it will have 32 sets of register for fast context switching. Since the RAM has two read/write ports the Harvard architecture will disappear.

Carbon_Rod

Thu Feb 16 2006, 06:39AM

Registered Member #65 Joined: Thu Feb 09 2006, 06:43AM
Location:
Posts: 1155

Very cool, B)
This book are OK if you need some low-level VHDL intro tips:
Vhdl Programming By Example
Douglas Perry

Also, we both know that often what works on one small chip will not scale-up to 74HCxxx series DIPs on a PCB. The old systems use to have almost a one-to-one ratio of filter caps to chip. What Clock speed did you want?

Note the French air-force did build a fully gate based U.A.V. a few years back.

Yep... Protel (now altium) used to sell a $2300.00 devel kit for in system fpga simulation on a real proto board. Now they say you do not even need to know VHDL to build a system (fpga Demo cost only a few hundred $ now):

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