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Registered Member #89
Joined: Thu Feb 09 2006, 02:40PM
Location: Zadar, Croatia
Posts: 3145
Hi guys,
Yes, but what I was trying to sense was the inverter's own output voltage with the transformer in parrallel. Before we continue, the point of the whole driver is making a SSTC driver which is 100% self-tuning with no room for human error. And which also makes sense using our theories on how Tesla coils work.
Ahh, the pin 3 and 4 short-cut. I measured the delay from pin 4 to the output voltage from my H-bridge and found it to be 300ns IIRC, at 700kHz that's approaching a 90 degree shift right there. Steve Ward's MKII PLL fixes it by allowing for a user adjustable delay, which has the benefit of allowing adjustment of the phase between the signals too, I think. Since I wanted all user adjustable features out of my driver to ensure a lock EXACTLY on fres I sense the inverter voltage directly. That is through the CT, because at resonance the inverter/primary voltage and inverter current AND the secondary current are all in phase. See where I'm going? A CT makes for a perfect inverter voltage phase feedback when used in a TC.
Oh, now I see what are you trying to do - basically eliminate all delay between VCO out and inverter out by sampling the inverter output voltage into pin 3, as you did in your IH circuit... but secondary base current has actually nothing to do with inverter output voltage, they are in phase only in resonance which must be achieved first through feedback! (note the absurd?)
So honestly I don't have much clue what is happening in your circuit, some scope shots and analysis would be very useful!
What I would consider to do would be to actually sample the inverter voltage, and use PC2, or some other means of canceling the 90 degree shift.
Regarding antenna vs. CT feedback, according to observations they are indeed same and swappable for each other. Antenna is a current source just like a CT; small portion of base current is fed into or sourced from it, as impedance between antenna and secondary base is low. Ignore any of my posts mentioning 90 degree phase shifts with antenna feedback like you used, that just doesn't seem true. See the lower parts of post;
BSVi wrote ...
Cool stuff! I amazed how simly you have got *prfect* tuning with dual feedback )
Just one question - why dont you use shottkeys and ultrafast diodes in your bridge ? Is it quick switch time of bridge's halfs that allows you to ignore slow fet's internal diodes recovery?
No, it is ZVS (class DE operation) that enables soft recovery of slow internal diodes, removing any need for additional diodes in properly designed SSTC. Dead time and lagging magnetizing current are critical for this, although in reality, through some weird luck typical SSTC's in frequency range 200..1000kHz operate in class DE fairly well with their usual primary inductance and small amount of deadtime provided by delays. Proper design should do better about deadtime than just adjusting gate resistors and eventually putting diodes in parallel with them, though!
Uzzors wrote ...
Since the bridge is switching a resonant load it's not much of a problem, but there's still magnetizing current which is hard-switched, so yeah I should maybe include some. The only reason they're not included now is because I don't have any.
Uzzors - hard switching of magnetizing current is GOOD, it is what actually removes the need of using additional diodes. External diodes should only be used if you are going to drive the coil below resonance, which is unlikely with a good feedback scheme. So, just don't worry about the diodes for now.
Richie:
An antenna near a working TC can either sense toroid voltage (E-field) or secondary base-current (displacement current from the toroid returning to ground) depending on what impedance the antenna is terminated into. There is a 90 degree phase shift between these two things so this means you have to use a different phase comparator or correct for the phase shift.
Ah, I was confused by these things as well. If my understanding is right:
..90 degree phase shift would be present on the antenna only if it was open circuit, or terminated by relatively low capacitive reactance.
I remember you explaining this to me this way: - since diodes represent nearly a short from antenna to secondary base, there won't be any significant phase shift between squarewave voltage at antenna and base current; basically, secondary base can be viewed as sourcing or pulling the current into antenna, producing in phase voltage at diode clamp midpoint.
In short, to my current understanding, antenna clamped by diodes gives no different output than a CT clamped by diodes.
Not sure if my understanding is full, but I also measured almost no phase shift between antenna feedback of this style and CT; the signals would always be in phase.
It is possible though, as far as I know, to produce a phase shift by a parallel capacitor on either antenna or CT as well - this is what Steve Conner did initially to combat 90 degree shift of XOR phase comparator.
So am I right Richie? I Still have the message you sent me about this, I can post it here if you allow.
I hope I don't appear invasive, I just want to remove myths and help my and others's understanding of this!
Registered Member #95
Joined: Thu Feb 09 2006, 04:57PM
Location: Norway
Posts: 1308
Lots of replying to do, let's see if I can address everything.
Dr. noob wrote ...
Oh, now I see what are you trying to do - basically eliminate all delay between VCO out and inverter out by sampling the inverter output voltage into pin 3, as you did in your IH circuit... but secondary base current has actually nothing to do with inverter output voltage, they are in phase only in resonance which must be achieved first through feedback! (note the absurd?)
Marko hit it dead on here, I wanted to make a driver with practically no delays and the nice self tuning nature of the buffer style TC drivers. The fact that the CT only works for inverter feedback when in resonance is pretty cheeky I agree, it's cool how PLL can just tune it like that. The other reason I made this driver is to better understand how PLL works, I now know how PC 2 and the MKII PLL drivers work. I did try VT feedback and PC2, but I couldn't clip the signal properly without killing things or losing the signal when at 650kHz. I could set it for a specific bridge voltage of course, but I wanted the driver to stand both low and full bridge voltages without adjustments.
I tried this driver on my old SSTC, which used Steve C's first PLL driver, because it had lost tune entirely when I fired it up yesterday. It worked perfectly with my new driver. Now the real mystery. My old SSTC has an isolated floating 12V supply, so the antenna should be an E-field feedback source, if I understood correctly. BUT, the coil you see in the pictures above uses a grounded to the secondary base logic supply! Now either this doesn't matter and the 4046 input gives a high enough impedance regardless (what about the diodes?) or something is wrong with the theory. Because the coil is working, is in "perfect" (hell, how much better can it get?) resonance, and I'm using an un-phase-compensated-for XOR comparator the phase difference must be 90 degrees.
Oscilliograms of whatever can be requested, my scope is limited to two channels.
Just for reference I had the coil working somewhat with PC2 and VT/CT combo feedback, but it would lose the lock too easily. I think the signals were just too noisy.
Registered Member #1637
Joined: Sat Aug 16 2008, 04:47AM
Location: Kiev, Ukraine
Posts: 83
Hi, Uzzors ) Would you be so kind to show me several oscillograms: 1) Voltage on pin 3 of PLL vs gate of nay transistor 2) Voltage on pin 14 vs gate of any transistor 3) Voltage on pin 3 vs voltage on pin 14 )
I have spent a lot of time trying to tune my sstc with PC2. It loses lock all the time ) Maybe its the reason to try your circuit )
Registered Member #95
Joined: Thu Feb 09 2006, 04:57PM
Location: Norway
Posts: 1308
I wish I could, but my scope died a few weeks ago just as I tried to scope the XOR inputs. The mains input fuse had opened. I hope to get it fixed eventually, or it may be a long time until I can investigate what's really happening. As for PC2, check what the input signals look like. They need to be very clean or PC2 will be fooled to think the frequency is much higher than it really is. Remember that with PC2 the signals must be in phase at resonance, so use primary voltage and secondary current feedback.
It's been a while since I've thought about this project, or PLL at all for that matter. (I've started at university! ) What I remember concluding with is this: You guys are worrying about the XOR creating a 0 to 180 shift throughout the frequency lock range, ie the locked phase difference is a function of where in the VCO range fres is at. This both makes sense and is mentioned in the datasheet for the 4046. However I haven't seen it happen in practice. My PLL IH driver uses this sort of driving technique, and is essentially no different from this circuit in any way. It works seemingly perfectly, even though fres is off to one corner in the VCO range (about 50% lower than the center frequency). How it can do that, I don't know and don't like. Using PC2 would eliminate the problem, but for now I'll leave this circuit as a curiosity.
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My PLL SSTC MKII (fresh new driver)
I did try VT feedback and PC2, but I couldn't clip the signal properly without killing things or losing the signal when at 650kHz. I could set it for a specific bridge voltage of course, but I wanted the driver to stand both low and full bridge voltages without adjustments.
I hope to get it fixed eventually, or it may be a long time until I can investigate what's really happening. As for PC2, check what the input signals look like. They need to be very clean or PC2 will be fooled to think the frequency is much higher than it really is. Remember that with PC2 the signals must be in phase at resonance, so use primary voltage and secondary current feedback.
) What I remember concluding with is this: You guys are worrying about the XOR creating a 0 to 180 shift throughout the frequency lock range, ie the locked phase difference is a function of where in the VCO range fres is at. This both makes sense and is mentioned in the datasheet for the 4046. However I haven't seen it happen in practice. My PLL IH driver uses this sort of driving technique, and is essentially no different from this circuit in any way. It works seemingly perfectly, even though fres is off to one corner in the VCO range (about 50% lower than the center frequency). How it can do that, I don't know and don't like. Using PC2 would eliminate the problem, but for now I'll leave this circuit as a curiosity.