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DRSSTC IGBT Gate Drive Problem

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GeordieBoy

Tue Jul 22 2008, 10:19PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

The core material, shape and dimensions are fine. It just has too few turns for 170kHz...

6T on a core with Al=2.25uH gives Lp=81uH.
With 12v drive applied for 2.9us, the primary current will ramp by 430mA. That current ripple figure is far too high for a GDT. The magnetising inductance is about a factor of 10 too small. Rewinding the primary with 3 times as many turns will get you 9 times the inductance. Hence my original ballpark suggestion of 15 turns.

Dr Conner: Your pictures at:

and

show text-book drive waveforms, and are a good example of the "Miller plateau" during the voltage fall phase of switching devices. Your comment "Well it's not really switching anything as the IGBTs aren't fully wired up" is interesting because I'm still not quite sure why you sometimes see the Miller Plateau when the DC bus is not powered. The power electronics textbooks say that ZVS eliminates the "Miller" effect in MOS gated devices because Vds (or Vce) is already zero at turn-on.

-Richie,

Timo

Wed Jul 23 2008, 03:32PM

Registered Member #1538 Joined: Thu Jun 12 2008, 07:28PM
Location: Bonn, Germany
Posts: 28

OK, hereâ€™s a little update:
Richie, you are right. I was just too lazy to calculate the current ripple. My first guess was a 12:24 GDT, but later I found that I could get faster rise/fall times by reducing the number of turns. But I didnâ€™t look at this overshoot before, so I didnâ€™t know if it was there with the first GDT. So I wound a new one, 15:30 Turns. Unfortunately there was no big difference. Have a look at it by yourself:

I also tried to change the film type DC-blocking cap back to an elko. In the next picture there is an â€œovershoot comparisonâ€. The upper trace is with the film cap, the lower with the elko, both using the old 6:12 GDT. The elko reduces the overshoot problem, but also increases the rise/fall times because of itâ€™s ESR. I will try a low-ESR type in the future.

(Donâ€™t care about the curser marks, I forgot to remove them)

Finally there is a picture made using the new GDT and the elko. Rise and fall times are even longer, but the overshoot is (nearly) removed.

I guess I will have to use this setup, although this means the IGBTâ€™s turn on at about 0.4*Ipeak, because it takes roughly 450ns from the prim. currentâ€™s zero crossing to the point in time when the rising gate voltage reaches V_threshold.
Or dose anybody have another idea? Maybe using IGBTs with a larger gate capacitance would help? Mine are very fast ones with a gate charge of only 70nC @15V. I thought it would be an advantage...

P.S.: thanks a lot again!

Timo

Thu Jul 24 2008, 11:31PM

Registered Member #1538 Joined: Thu Jun 12 2008, 07:28PM
Location: Bonn, Germany
Posts: 28

Hello again

For those who did not get bored jet: I think I found a way to get rid of the overshoot problem without increasing the rise-time a lot. I did the following:
For sure you all know the method of introducing dead time by charging the gates through a resistor (10 Ohm or something like that) and discharging it through a diode connected in parallel. I knew that increasing this resistance would cure the problem by increasing rise time. Fall time, however, may remain short, because an overshoot in falling direction can not turn on the IGBT.
Having this in mind, I came up with the idea of changing the diode into a Zener-diode. I thought this way I could charge the gate fast from â€“30 to, say, -5 volts by using the diodes ability to carry nearly any amount of current as long as there is a sufficient voltage difference. At this point the voltage across the Z-diode would have dropped enough to stop the avalanche/Zener effect. The resistor would now be the only way to charge up the gate further. Using the right resistor should slow the voltage rise sufficiently to prevent the overshoot, while saving the time it would have taken to charge from â€“30V to â€“5V only through the resistor.

However, things turned out to be even more beautiful. I found that I could charge nearly all the way to +30V through the Zener. Only a few volts of resistive charging (say, from +25V to +30V) are needed to prevent the overshoot.
In the next picture you see the gate being charged nearly exclusively through the Z-diode. The last ~5 volts are added using a 100 Ohm! resistor. This rounds of the upper left edge of the lower trace a little. Trace 1 is a â€œnormal chargingâ€ reference.

Next Picture. I measured the delay between â€œnormal chargingâ€ (Schottky diode + 10 Ohm) and â€œZener chargingâ€ (Z-diode + 100 Ohm). As you see itâ€™s roughly 50ns around V_threshold, which is a lot better than it was with the setup used for the third image of my last post.

And finally, for the sake of completeness, here is a picture of the voltage over the Zener during the charging process. Upper trace is the gate voltage, of course.

So, before I get to optimistic: dose anybody see a drawback? If not I would give it a tryâ€¦

GeordieBoy

Fri Jul 25 2008, 10:33AM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

You don't necessarily want a blazing fast turn-on as it can tend to cause transients and ringing in switching circuits. Also remember that the switching devices are only in the linear region for a small portion of the slope on that gate-voltage waveform you show here, so the switching times are not the full 10%-90% rise- and fall-times of the gate waveform.

One final thing to remember is that this all changes when the power devices are actually switching some real current. So don't take too much time looking at waveforms gathered when not under power. It's the ones under-power that matter.

Dylan

Sat Jul 26 2008, 12:45AM

Registered Member #1024 Joined: Sun Sept 23 2007, 10:56AM
Location: Northern NSW, Australia
Posts: 95

Hi Timo,
I like the zener/resistor gate charge idea! Nice one.
I am curious however, can you capture or describe the waveform at this moment across the input side of your GDT (ie at the output of your driver chips)?
I suspect you may see a very short pulse occuring at the end of your interrupter on time, as I have seen this in simulations of a j-k sychronised driver.

Timo

Sun Jul 27 2008, 06:59PM

Registered Member #1538 Joined: Thu Jun 12 2008, 07:28PM
Location: Bonn, Germany
Posts: 28

Richie, of course, I have to agree with you again. But Iâ€™m not that much concerned about the time it takes to turn the IGBTs on. Iâ€™m concerned about the current flowing in the prim. circuit at that point in time when the gate voltage passes V-threshold. Wouldnâ€™t it be a benefit to turn on at 0.2*I_peak instead of 0.4*I_peak? A faster rise time would particularly turn the IGBTs on earlier.

To reply to your post, Dylan, Iâ€™m pretty sure I know what youâ€™re talking about. I made a picture of the Ucc driver chips output, referenced to ground.

The upper trace obviously has a short peak just before both drivers go low because theyâ€™re turned off via their enable pins. I think this is due to the flip-flopâ€™s propagation delay. In my case, the Uccâ€™s input signal is also used as the flip-flopâ€™s clock. The flip-flop drives the enable pins with a small delay, referenced to the clock signal. I tried to take a picture of this delay, but it is difficult. The falling trace is the voltage at the enable pins, the rising one is the clock/drive signal.

As you see the enable pins voltage dose not change for about 10ns after the clock signal started changing. However, the rise and fall times are even longer, so there is a lot of room for interpretations.
You could try to reduce this delay by using faster logic ICâ€™s, like 74ACxxx / 74ACTxxx, but I wouldnâ€™t recommend that, because they tend to be more sensitive to any kind of noise.
Another way would be to add some kind of delay in front of the driver chips, but behind the flip-flopâ€™s clock input.
In any case this small peak doesnâ€™t matter at all, because it is too short to have any significant effect to the gate voltage. The pulse will be over before the gates have reached 0 volts, and if it dose anything, than it helps to get there faster.

Timo

Steve Ward

Mon Jul 28 2008, 12:49AM

Registered Member #146 Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055

You never really specified what IGBT you were using here? Id be curious to see if you simply are expecting too much speed from the device. 170khz is rather high for most IGBTs, so if you were trying to use some brick sized ones, that could explain a lot.

Is there some reason you would not just wind a secondary with a lower resonant frequency?

Also keep in mind that the turn on transition isnt really all that bad. Its just interrupting the current flowing through the reverse diodes. You will get a "snappy" recovery, resulting in voltage transients on the bridge, but from what i can tell, these dont seem to be terribly dangerous if you keep your Vbus at about 1/2 the device rating.

Timo

Mon Jul 28 2008, 04:15PM

Registered Member #1538 Joined: Thu Jun 12 2008, 07:28PM
Location: Bonn, Germany
Posts: 28

Hmm, ok, may be I was to careful reducing turn-on current...
And to answer the IGBT question: at the moment I'm using the FGH50N6S2D, a quite fast one, but I realised this was not the best choice. However, I would like to use something in a To 247 (or similar) package because otherwise I would have to rebuild the fullbridge. I also tried the STGW39NC60VD and the HGTG20N60A4D. After blowing a lot of IGBTâ€™s at about there rated I_pulse I decided it was time to improve my driver. I thought the turn-on might be the problem, because all the other parameters seemed to be close to the device ratings.

I will be buying new IGBTâ€™s soon, so maybe someone could give me an advice? I lately found the SGL160N60UFDTU. It looks like a rather fat device for itâ€™s package (itâ€™s a To264 one, but I hope it will fit).

And to answer the question about winding another secondary: of course that wouldnâ€™t be a problem, but the setup already worked fine for some time. I thought it was time for troubleshooting, not for a complete redesign.
I have uploaded a video of my results so far to youtube. >This< was with my last complete set of STGW39NC60VD, before the bridge blew up.

Steve Ward

Mon Jul 28 2008, 06:00PM

Registered Member #146 Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055

Oh, the FGH50N6S2D is a very fast IGBT. I used them to switch my 1.2MHz DRSSTC, but i never pushed the current too high. I agree, your turn on delay time seems excessive, i remember having it down to <100nS with similar IGBTs, without much special attention to how things were put together.

I havent worked with 247 sized IGBTs much, but i didnt have very reliable results when i did. Having learned a lot since then, id like to give them another go and see if i do any better. Its hard to say what might cause the failure, but my guess would be that the die temp is spiking too high, either from poor thermal conductivity to the heat spreader, or simply pushing them too hard.

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