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Registered Member #1024
Joined: Sun Sept 23 2007, 10:56AM
Location: Northern NSW, Australia
Posts: 95
So , sounds like there is a benefit to being able to set the maximum duration of the startup ( I've been calling it boot) pulse. Not that I have any idea of the details , just had a gut feeling. And I was thinking of limiting it to 1/2 duration , not quater, but hey , I'll give 1/4 a go. I should also clarify what I mean by '1/2Fres', as I think my terminology is confusing everyone, I mean 1/2 period of the resonant frequency, ie the duration of each pulse provided by the GDT driver. ie: _-_-_- <-resonant freq _ <-duration of 1/2 period of Fres
Also , I'm still not convinced Steve, about the gate drivers at boot pulse either : Starting via enable pin (ie both start low) ___----___ ______---- vs: enable pin always high, (ie both always opposite) ___----___ ----___----
Surely there is a difference at the output of the GDT between these two initial pulses? One involves a transition of X volts, the other only 1/2X volts. I just cant see how the output could or should be the same in both these cases, not that I'm insisting I'm right, I just still don't see it.
Also I feel the same would apply when using the enable pins to terminate output at the end of the interrupter cycle, ie one of the drivers will stay in its current state (the one already at 0v), the other will transition to 0V, as opposed to the drivers simply NOT transitioning again. ie : Using enable pin on termination of interrupter burst: ___---___---___---___ ---___---___---
______ -------------------^Terminus Vs:
Terminating via logic of drive signal: ___---___---___------ ---___---___---
______ -------------------^Terminus
And again , many thanks for all the advice and input!
Banned on 3/17/2009. Registered Member #487
Joined: Sun Jul 09 2006, 01:22AM
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Posts: 617
I would just like to add. I dont know what IGBT's you plan on driving but if they are to-247 packaged I think 4 gate drive chips is insane overkill. I use two chips to drive two GDT's. GDT's are in parallel and since the circuit is pulsed the driver should have plenty or power.
Registered Member #1024
Joined: Sun Sept 23 2007, 10:56AM
Location: Northern NSW, Australia
Posts: 95
:) very true Tom. But I was just trying to make the PCB layout more flexible , I figured I could simply run with one pair OR two pairs. I will be driving 247/TO-3p mostly , but also have a big fullbridge of bricks I want to try it out on. And yes everyone , I realise driving the bricks with a GDT and four UCC's will be , shall we say, a challenge .
Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
Also , I'm still not convinced Steve, about the gate drivers at boot pulse either : Starting via enable pin (ie both start low) ___----___ ______---- vs: enable pin always high, (ie both always opposite) ___----___ ----___----
Surely there is a difference at the output of the GDT between these two initial pulses? One involves a transition of X volts, the other only 1/2X volts. I just cant see how the output could or should be the same in both these cases, not that I'm insisting I'm right, I just still don't see it.
Your second method proves problematic, for at least one reason... how do you end your pulse train to end up with them at different levels? That would mean your last IGBT switching event would have to naturally decay off.
Also, in your second drawing, you would indeed be forcing 2X the voltage, but here is the catch.... your IGBT gate is at 0V initially, so youd blast it with 2X Vcc. Remember, when its oscillating, the IGBT gate turns off to -Vcc... not just zero. That should put an end to all this .
Richie's talks about magnetic flux walking, while quite true, is easily overcome by 1) using a big DC blocking cap (i use like 20uF ceramic for driving big bricks through GDTs), and 2) using a parallel damping resistor to the blocking cap. I haven't tested extremely long pulse lengths yet, so im not sure if the problem would truly get out of hand (in a practical sense) if you tried to drive the coil for say 100 cycles.
Im not digging all the extra crap to go wrong with special start up circuits and stuff. If ive learned anything about making these things robust, its making them work with the simplest possible control system, and focusing on making that system robust.
Registered Member #1024
Joined: Sun Sept 23 2007, 10:56AM
Location: Northern NSW, Australia
Posts: 95
Steve Ward wrote ...
Your second method proves problematic, for at least one reason... how do you end your pulse train to end up with them at different levels? That would mean your last IGBT switching event would have to naturally decay off.
Also, in your second drawing, you would indeed be forcing 2X the voltage, but here is the catch.... your IGBT gate is at 0V initially, so youd blast it with 2X Vcc. Remember, when its oscillating, the IGBT gate turns off to -Vcc... not just zero. That should put an end to all this .
Ahh, yes , ok , I agree. Ending the pulse train with both drivers (All gates) low = good. Ending the pulse train with one gate (or 2 in Full bridge) high and letting the gate decay via the GDT winding = bad.
I'm not sure your second point here is correct. Assuming we take the IGBT emitter (and one end of the GDT winding) as fixed at 0v, my boot pulse will simply drive the gate to the same voltage as any other pulse in the train. As opposed to the gate only beign driven to half the voltage of the normal pulse train. The fact that the gate is starting at 0v simply means the initial rise time will be faster than if it was at -V as it is during oscillation, as opposed to slower. I can only see this as a good thing.
I dont really see that my circuit so far has added any signifigant complexity, but I do definately aggree with the Keep It Simple principle.
Mmm , but how to have a full boot transition AND both drives low at pulse train end !?! Now theres a problem!
Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
I'm not sure your second point here is correct. Assuming we take the IGBT emitter (and one end of the GDT winding) as fixed at 0v, my boot pulse will simply drive the gate to the same voltage as any other pulse in the train. As opposed to the gate only beign driven to half the voltage of the normal pulse train. The fact that the gate is starting at 0v simply means the initial rise time will be faster than if it was at -V as it is during oscillation, as opposed to slower. I can only see this as a good thing.
No, no no... Use your same "delta V" logic as from before. Initially (that is, when the IGBT has been off for a long time, between bursts), IGBT Vge is 0V. If one driver transitions, the delta V is 1*Vcc, so the Vge jumps to 1*Vge. Your proposed "switch both drivers" will have a total of 2*Vcc for a delta V, thus the Vge will jump from 0 to 2*Vcc.
In fact, your method of making both drivers transition at start will give your GDT a truly nasty DC offset bias. Dont make me whip out p-spice simulations to prove this... i will do it!
The reason you can have both drivers transition during the rest of the cycles is that the IGBT Vge is either +Vcc or -Vcc, so it has to transition 2*Vcc. Again, this is NOT the case for the very first and very last transitions, where you are returning to 0V Vge.
So unless there is still a communication break-down here, i am right and will never be convinced otherwise . But seriously, my logic should make sense.
Registered Member #1024
Joined: Sun Sept 23 2007, 10:56AM
Location: Northern NSW, Australia
Posts: 95
No , sorry , still not convinced. All I am proposing is to drive ALL pulses with the same V, my origional logic holds. The gate is not a diode pump voltage doubler, the voltage on the gate will be driven to match the voltage on the GDT. Regardless if the gate started at 0v or -10v or +10v.
Might need a third party umpire on this one
I also wonder how you reconcile your last post with your earlier ones ie:
Steve Ward wrote ...
Ignore the capacitor... if its properly sized it will behave like its not there. The first pulse will provide +Vcc, or -Vcc on the gates (phasing dependent) and not half the normal drive voltage or anything weird. The GDT really does behave as if you connected the IGBT gate to one driver and the IGBT source to another driver... no voltage division or anything (unless your GDT is something other than 1:1 ratio).
Also as far as your earlier point about the end mode:
Steve Ward wrote ...
Your second method proves problematic, for at least one reason... how do you end your pulse train to end up with them at different levels? That would mean your last IGBT switching event would have to naturally decay off.
I no longer agree that this is a problem unique to my design: As far as I can see, EVERY driver that uses a GDT would have this problem! Regardles of the terminal DC state of the drivers on the input side of the GDT, the last pulse provided by the GDT will leave two (full bridge) gates in the bridge to decay from their on state. If this has not been a problem for every GDT driven bridge yet made , then I can only assume its , well , not a problem.
And as far as DC-bias , this is exactly the benefit of having a driver with limited duration boot pulse , as eloquently detailed earlier in the thread by Richie.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
I'd normally ignore you guys completely, but I can't sleep and have nothing better to do :P
All of your misunderstandings are connected as follows.
In our classical drivers controlled via the enable pin, the net charge on the DC block capacitor is nearly zero. It only departs from zero if you switch an odd number of half-cycles, or if the GDT saturates slightly on the first half-cycle, which it may well do as Richie explained. Either way, it doesn't stray far from zero and easily decays back. Unless a feedback driver fails to "boot", which is a valid concern, and another reason why I started using PLLs. They can screw up in a lot of other ways, but the oscillator keeps going, feedback or not.
Now for Dylan's switching schemes. In order to start a burst with the driver outputs in opposite polarities, that must be their steady state. (A DRSSTC spends 98% of its time off.) Since the GDT primary is an inductor, it can't support any steady voltage, therefore the only way to reach this steady state is for the DC block capacitor to charge to a voltage equal to the gate driver output. In other words the only way to get into the state is to have the last switching event of your previous burst "decay", as you put it.
On the first pulse of the new burst, this charge will add to the gate driver output, since it opposed it before. So one device in a half bridge would see twice the normal gate voltage while the other gets none and won't turn on at all. This will oscillate or decay back to proper operation as the DC block cap discharges, no doubt leaving plenty time to mess it up again for the next burst.
Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
I dont care to carry on this "debate" any more. Prove whatever you want to yourself Dylan, im not sure where our misunderstanding is exactly. Ive tried to be perfectly clear and consistent with my thinking, but this has not come across apparently.
I believe Conner supports my reasoning as well.
BTW, dont you currently have a working DRSSTC? Cant you go and scope your gate drive circuit?
Registered Member #1024
Joined: Sun Sept 23 2007, 10:56AM
Location: Northern NSW, Australia
Posts: 95
Oh dear. This appears to have become personal. Steve , I sincerely apologise if you feel I have been in anyway attacking you personally, that was not my intention at all. I am merely trying to find concrete answers to design questions. You are quite right I do have more than one working DRSSTC, none however using this new driver scheme. When I get my new boards and finnish the driver I will be checking all the relevent waveforms carefully. Perhaps its best if we leave it at that for now, and when I have the results I will post them.
Again thanks to everyone who has contributed so far.
On a final note, I can see how it must be frustrating for many of you with more knowlege and experience , trying to explain such technical issues to beginners such as myself. I know I'm stubborn, and I demand not to simply believe , but to understand, and that can make me seem confrontational , especially in the context of a forum. I can assure you all I do appreciate all your comments.
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New driver design ideas
, just had a gut feeling.
