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Registered Member #1024
Joined: Sun Sept 23 2007, 10:56AM
Location: Northern NSW, Australia
Posts: 95
Hi all , I've been messing around with some driver ideas, let me know what you think.
Assuming a flip flop synchronised driver, with push pull GDT drive using your chosen flavour of gate drive chip:
- When the initial gate drive pulse starts , if it has been started by bringing up an enable pin on the gate drivers, then that first pulse will effectively be driven single ended as one of the drivers transitions but not the other (both low when enable low). So ideally we should avoid using the enable pin in this way.
- Most drivers rely on feedback to terminate the first 'pulse' and begin oscillation, as the 'pulse' is infact a 'Busrt lenth' high signal effectively XORed with the feedback. This theoretically leaves the chance that the first pulse may be longer than the ideal period of 1/2 resonant wavelenth, if feedback fails it will in fact be the full 'Burst length'. So ideally our drive would be a 'Burst length' signal ANDed/NANDed with feedback, and we supply a 'Boot' pulse of 1/2Fres period to kick start oscillation.
===== Not tackling this yet ===== - Secondary feedback is great as you are always driving in tune with the secondary. Primary feedback is great for saving output devices as you are always driving at zero crossing on the primary side. So most people seem to use primary feedback and carefully tune the Fres of the primary and secondary circuits. But surely it would be better for the driver to at least attempt to synchronise the two, so use BOTH primary and secondary feedback, attempting to lock on to the secondary within a safe window of the primary. ===== End Not tackling this yet =====
Anyway , thats my thoughts for now, I'm currently brewing up a driver to try these ideas out on , just finnished the layout (attatched). Will let you all know how it goes.
Banned on 3/17/2009. Registered Member #487
Joined: Sun Jul 09 2006, 01:22AM
Location:
Posts: 617
I'm a little lost without a schematic as far as how it works.
Your layout looks pretty good except I think you should ad some thermal reliefs to the right side of your board where the output caps and diodes are etc. Just a thought, might be tough to solder but might not matter either.
Registered Member #1024
Joined: Sun Sept 23 2007, 10:56AM
Location: Northern NSW, Australia
Posts: 95
Cheers Tom , yep I decided against thermal pads on all the output stuff, figured I'd preffer a really good contact and put up with the soldering pain. As far as being a little lost , now that I read it again , so am I :) , I know exactly what I'm trying to say , but I started the thread a 1:30am , and with a few red wines under my belt.
I will post some schematics and more readable descriptions soon.
Registered Member #1024
Joined: Sun Sept 23 2007, 10:56AM
Location: Northern NSW, Australia
Posts: 95
Ok , this may describe problem 1 a bit clearer: Were looking at the standard GDT driver setup using UCC27xxx chips or similar.
~~ Say feedback takes 3 units of time to 'ring up'.
Using enable pins (to get inherent boot pulse) for Interrupter signal and driving with feedback signal only:
GD Enable Pins : ___--------------____ (Interrupt)
GD Input pins : ______-_-_-_-_-_-_-_- (Feedback)
Highside GD Output : ______-_-_-_-_-_-____
Lowside(INV) GD Output: ___---_-_-_-_-_-_----
^ Boot pulse is only V*1 delta
As opposed to providing the combined feedback, Interupter and boot pule signal to always enabled drivers :
GD Enable Pins : ---------------------
GD Input pins : ___---_-_-_-_-_-_____ (Feedback + boot pulse + Interrupt)
Highside GD Output : ___---_-_-_-_-_-_____
Lowside(INV) GD Output: ---___-_-_-_-_-_-----
^ Boot pulse is V*2 delta
Banned on 3/17/2009. Registered Member #487
Joined: Sun Jul 09 2006, 01:22AM
Location:
Posts: 617
The thermals aren't really a big deal but not using them is just overkill on a driver board. I use 4 50mil spokes on my IGBT bridge thermals without problems. I have all power layers doubled up on top and bottom for a total of 8 thermals per IGBT pin. If you can solder it without problems then leave them out.
Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
- When the initial gate drive pulse starts , if it has been started by bringing up an enable pin on the gate drivers, then that first pulse will effectively be driven single ended as one of the drivers transitions but not the other (both low when enable low). So ideally we should avoid using the enable pin in this way.
So? One driver is actively sourcing current and the other is sinking current. There is no problem.
- Most drivers rely on feedback to terminate the first 'pulse' and begin oscillation, as the 'pulse' is infact a 'Busrt lenth' high signal effectively XORed with the feedback. This theoretically leaves the chance that the first pulse may be longer than the ideal period of 1/2 resonant wavelenth, if feedback fails it will in fact be the full 'Burst length'. So ideally our drive would be a 'Burst length' signal ANDed/NANDed with feedback, and we supply a 'Boot' pulse of 1/2Fres period to kick start oscillation.
Once again, dont care. The GDT will saturate before then and turn off the transistors. Oscillation is basically guaranteed in most cases. If it fails, then you are driving way off resonance so the currents will be low (provided dual-resonant setup, or at least a DC-blocking cap).
- Secondary feedback is great as you are always driving in tune with the secondary. Primary feedback is great for saving output devices as you are always driving at zero crossing on the primary side. So most people seem to use primary feedback and carefully tune the Fres of the primary and secondary circuits. But surely it would be better for the driver to at least attempt to synchronise the two, so use BOTH primary and secondary feedback, attempting to lock on to the secondary within a safe window of the primary.
There is again no point to this. Just tune your primary circuit properly.
Im only being "close minded" here because i run these systems for live demo's for hours on end, and they always work just fine. Id suggest avoiding all of the extra complication added by your proposed improvements since for the most part they are unnecessary.
Registered Member #1024
Joined: Sun Sept 23 2007, 10:56AM
Location: Northern NSW, Australia
Posts: 95
Points taken. I came up with a basic scheme something like the attatched pic. But all those gates will definetly add delay I guess, It should however both: 1: Ensure ALL GDT transitions are 2*Vcc delta 2: Supply a boot pulse with a settable maximum duration (ie:close to resonance) , with feedback overriding and terminating the boot pulse. Naturally the and buffer at the end could have more ins for OCD and so on, this is just the basic idea.
It is probably all unnessecary , but Im going to build it anyway, after all who ever said it had to be nessecary
Oh , and I've given up on dual Pri/Sec combined feedback for now, not sure what I was smoking when I decided to tackle that :)
Steve Ward wrote ...
- Most drivers rely on feedback to terminate the first 'pulse' and begin oscillation, as the 'pulse' is infact a 'Busrt lenth' high signal effectively XORed with the feedback. This theoretically leaves the chance that the first pulse may be longer than the ideal period of 1/2 resonant wavelenth, if feedback fails it will in fact be the full 'Burst length'. So ideally our drive would be a 'Burst length' signal ANDed/NANDed with feedback, and we supply a 'Boot' pulse of 1/2Fres period to kick start oscillation.
Once again, dont care. The GDT will saturate before then and turn off the transistors. Oscillation is basically guaranteed in most cases. If it fails, then you are driving way off resonance so the currents will be low (provided dual-resonant setup, or at least a DC-blocking cap).
Im not sure you got me here , when I said: "This theoretically leaves the chance that the first pulse may be longer than the ideal period of 1/2 resonant wavelenth, if feedback fails it will in fact be the full 'Burst length'." I am aware that the pulse length at the output of the GDT is in fact limited by the GDT as well, Im talking about at the input of the GDT. And I would hope that the GDT does not saturate faster than, or even close to 1/2Fres, surely it should be capable of far longer pulses that the intended pulse length?
As far as 'don't care', I understand, I'm just a little obsessive , and if its a system that is even a little closer to the ideal behaviour, I'm prepared to give it a go.
Steve Ward wrote ...
- When the initial gate drive pulse starts , if it has been started by bringing up an enable pin on the gate drivers, then that first pulse will effectively be driven single ended as one of the drivers transitions but not the other (both low when enable low). So ideally we should avoid using the enable pin in this way.
So? One driver is actively sourcing current and the other is sinking current. There is no problem.
I may very well be wrong, but with a capacitively coupled GDT , I would have thought driving a pulse at 1/2 the Vdelta would give half the V out ? I am prepared to stand corrected here, as everywhere.
Tom540 wrote ...
The thermals aren't really a big deal but not using them is just overkill on a driver board. I use 4 50mil spokes on my IGBT bridge thermals without problems. I have all power layers doubled up on top and bottom for a total of 8 thermals per IGBT pin. If you can solder it without problems then leave them out.
Advice taken , I'm new to PCB layout so I was just playing it safe, but if its no problem then thermals it is!
A bit of shuffling to give an input for OCD (tied high for now) without adding any components , well ok , the pullup resistor.
[MOD NOTE]
Double Posting is not allowed. Especially (5) Posts in a row. Please read the rules regarding posting.
** Sorry ED , I'll behave, thanks for combining my posts, I just edited it to fix a broken block-quote.
Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
Im not sure you got me here , when I said: "This theoretically leaves the chance that the first pulse may be longer than the ideal period of 1/2 resonant wavelenth, if feedback fails it will in fact be the full 'Burst length'." I am aware that the pulse length at the output of the GDT is in fact limited by the GDT as well, Im talking about at the input of the GDT. And I would hope that the GDT does not saturate faster than, or even close to 1/2Fres, surely it should be capable of far longer pulses that the intended pulse length?
This depends on your design mentality. I believe in winding my GDTs so that they have only a small headroom for saturation, that means using the least turns possible to keep resistance and stray inductance down. My GDTs likely wouldnt work at 1/2 Fres.
When the GDT saturates, the DC blocking cap takes up the slack in keeping the driver current down, by ummm... blocking the DC saturating current :P.
I may very well be wrong, but with a capacitively coupled GDT , I would have thought driving a pulse at 1/2 the Vdelta would give half the V out ? I am prepared to stand corrected here, as everywhere.
Ignore the capacitor... if its properly sized it will behave like its not there. The first pulse will provide +Vcc, or -Vcc on the gates (phasing dependent) and not half the normal drive voltage or anything weird. The GDT really does behave as if you connected the IGBT gate to one driver and the IGBT source to another driver... no voltage division or anything (unless your GDT is something other than 1:1 ratio).
Registered Member #1232
Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881
The first pulse into a GDT *SHOULD* actually be a quarter cycle long, then followed by alternate half-cycles in either direction. This would actually keep the magnetising current symmetrical about zero, and the flux excursion of the core symmetrical too.
If the first pulse isn't half the duration of the others, then the magnetising current will integrate up to some positive or negative value. This DC component would persist if it were not for the DC blocking capacitor that reduces it to a decaying oscillatory transient, usually at a frequency much lower than the switching frequency. The damping resistors Steve W mentioned across the DC blocking cap help to further reduce this oscillation to a brief decaying transient.
The same comments hold true for a conventional SSTC (not DRSSTC) where the primary is driven directly from an H-bridge in burst mode. The first pulse should be halved in duration to ensure symmetrical magnetising current, and to ensure even current sharing between the switching devices.
If this is not clear, a quick simulation with a pulse generator, current-sense resistor and an inductor all in series clearly shows the behaviour.
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New driver design ideas
, and if its a system that is even a little closer to the ideal behaviour, I'm prepared to give it a go.
