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Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Your idea might well work as most IGBTs are short circuit rated for 10us, which isn't that far off one cycle. I could never be bothered implementing desaturation detection though. The main problem is that we use the devices at much higher frequencies than they were intended for, so the di/dt voltages across the package inductance get high enough to fool the usual desat circuits.
Also, the most likely cause of desaturation is that the opposite bridge leg has just failed short. When using half-bridge modules, you have to throw the whole module away at this point anyway, so it's not worth the bother stopping the failure from cascading. With large single devices like the CM600, it might be worthwhile.
The cycle skipping current limit is nice, but it's skipping somewhat more cycles than I'd have liked. :< Maybe the primary needs to be higher impedance still. Will be interesting to see what happens when the OCD is turned up after next Friday.
The cycle skipping current limit is nice, but it's skipping somewhat more cycles than I'd have liked. :< Maybe the primary needs to be higher impedance still. Will be interesting to see what happens when the OCD is turned up after next Friday.
I was thinking along the same line. Where is loaded Q at now? Did you observe any frequency jumps?
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
I think the loaded Q is around 6.
The PLL can't track an instantaneous jump, and I didn't notice any extreme hard switching, so I don't think there were any frequency jumps. As the loading increases, the frequency probably collapses from the upper pole to somewhere around the middle of the passband.
I wonder if performing a STFT of the primary current waveform would shed any light on this? Is there any way to "deconvolve" the frequency spectrum of the driving voltage from the current, to get the impulse response of the resonator at a given point in time?
As long as there is no hard switching, the input to the VFO should be a good indicator of zcs frequency. Running the coil at some lower Vbus to avoid pulse skipping might also help analysis. Dunno if a STFT would help. There's always a delay between primary current and the secondaries response to it.
Edit: You could do a STFT on both primary voltage and current and divide them, which gives Z in the frequency domain.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Ooh, good idea, I think I will try that.
I measured the distance from the breakout point to the little burnt spots on the ceiling, 1.8m. So I haven't beaten the 2.1m output of the OLTC2 yet, but I don't think this will be too hard.
Been thinking about the frequency jumps, since they might be harmful to the electronics. I believe the jumps to happen only in the case, when, at the time Qsec drops below 1/k, primary fres is still below secondary fres. If secondary fres is then lower than primary fres, there will be no jumps. Where are the unloaded resonances?
My guess is then, that primary and secondary fres are quite close to each other. With arc capacitance secondary fres would drop below primary fres and you won't see any frequency jumps. Lowering primary fres will probably reduce pulse skipping at the risk of getting frequency jumps.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Yes. I started out with the primary and secondary tuned the same, and have been lowering the primary fres for each test run. Each time I lowered it, the amount of pulse skipping at full power decreased, and the spark output got bigger. On the last run, the pulse skipping duty cycle was up to about 75%.
Interestingly the detuning decreased the spark output at very low power. When I ramped up the DC bus voltage slowly from zero, the earliest breakout seemed to occur with the two coils exactly in tune. Any detuning delayed it, but once breakout happened the spark growth was more impressive.
I will continue to detune with each run until I run out of primary turns or the performance starts to fall off. Once I run out of primary turns, I could add more tank capacitance, but I guess that might be counterproductive as it would lower the impedance of the tank circuit?
Interestingly the detuning decreased the spark output at very low power. When I ramped up the DC bus voltage slowly from zero, the earliest breakout seemed to occur with the two coils exactly in tune. Any detuning delayed it, but once breakout happened the spark growth was more impressive.
That's unexpected from theory. The ordering of frequencies at low power from low to high would be: flow, fpri, fsec, fup, for lower pole, primary fres, secondary fres and upper pole. Lowering fpri should move fup, i.e. the f you're running on, closer to fsec, which would decrease Qpri and so lead to earlier breakout. I should redo the math here.
At large arc capacitances fsec drops below fpri, but fup still reamains above fpri, which increases the fup to fsec difference and thus increases Qpri. Lowering fpri will allow fup to follow fsec closer and so keep Qpri lower.
Once I run out of primary turns, I could add more tank capacitance, but I guess that might be counterproductive as it would lower the impedance of the tank circuit?
Yes, I think so too, but you might get away with increasing the MMC. There are 2 effects countering each other, lowering fpri, which decreases Qpri and decreasing tank impedance, which increases Qpri.
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Odin The All-Fragger: a large DRSSTC
