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Registered Member #4465
Joined: Wed Apr 18 2012, 08:37AM
Location: Bucharest, Romania
Posts: 145
Thank you for the advice.
On the other hand, based on the Wolfram’s design, I was temped to squeeze the complete Control Circuit into my 8x10 cm two layers MOSFETs Drive PCB. I have spent some time struggling with the Eagle Light Edition limitations, and finally I have decided it’s time to switch for more functionality and to upgrade. I have attached the four layers PCBs version.
Registered Member #33
Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971
Nice work. It felt very nice going to four layers, it gives a lot more freedom, especially around the bridge where wide traces are needed for high current. I found out that the board house I use have thinner copper for the inner layers, half the normal thickness, so keep in mind that this will lead to higher than expected I^2 * R losses in the inner layers if you assume they are equal to the outer layers.
Your bootstrap diodes on the HV side of the silabs drivers look very big. I'm a bit worried that such a big diode will have a significant reverse recovery charge so that it will steal some voltage from your bootstrap capacitor when the upper FET/IGBT switches on. This diode only needs to carry the small current to supply the upper gate driver. The main importance is that it needs to handle your DC bus voltage and it needs to be fast.
I feel honored that you've based it on my circuit. Do you have a schematic you can post? Keep in mind that I haven't tested my design completely yet, so I cannot guarantee that everything is 100% correct. My working prototype is a much earlier and simpler version. I'm currently working on putting together some boards that are much closer to the final version, but the last days have been a bit too busy and I haven't tested them yet.
My previous calculation of the flux density was incorrect, the real flux density is only half of what I said earlier, so losses will be much lower and two cores will work fine. This is also great news for my design, as I based my designs on the wrong calculations also. This means that I can get away with much smaller coupling transformers than I expected.
Edit: I don't immediately notice any capacitance across the bridge. I would recommend a few microfarads of polypropylene caps here. With ZCS it is a lot less critical than a hard-switched bridge, but there's still some significant ripple current drawn from the DC bus, which needs to be supplied from somewhere. Having these caps on the board will minimize any voltage drop due to wiring inductance and also the potential for EMI.
Registered Member #4465
Joined: Wed Apr 18 2012, 08:37AM
Location: Bucharest, Romania
Posts: 145
As a matter of fact, I had already considered that aspect. For the bootstrap diodes I have in plan to use some Silicon Carbide Schottky Diode. (C3D02060F/ C3D03060F).
For the future use I have placed some SMDs diode/ resistor pads on the PCBs bottom layer also.
About the schematics, for the moment that’s a little bit too messy. That schematic was compiled in the old software from previous fragments designs, in order to get rid of the 8x10cm size limitation, but to improve the PCBs design, and will take some time so rearrange it. Anyway, don’t expect too many changes compare to your original design.
And on that PCB I don’t have installed the AC/DC module (including the HALL effect current sensor circuit).
There’s another issue for the moment, and maybe I need to keep to the standard 2 layers PCBs. The production price for the 4 layers is up too high for my personal demo. I’ll plan to put in production a small batch of 5 boards, in order to use one piece and later on, to decide if my personal experiments require such upgrade.
Registered Member #4465
Joined: Wed Apr 18 2012, 08:37AM
Location: Bucharest, Romania
Posts: 145
A final 3D image of the new PCBs just lunched in production, using a handy online free viewer tool. You can upload your Gerber files and have a 360 degree view of the PCBs design here: I manage to squeeze also the small auto ranging 3-digit frequency counter, and just in case I need, for future modifications two ICs spare slots.
Registered Member #33
Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971
Looks good. I always use that 3D gerber viewer before sending boards to production, it makes it so much easier to see problems in the board design and in the gerber files. Recently I've started using ZofzPCB which has even more options.
I was looking into using SiC devices now, as they are superior to IGBTs in switching characteristics, and there's one thing that worries me a bit. The reverse diode is very fast, but the forward voltage drop is significantly higher than I expected.
While writing this post I realised that the reverse voltage drop might be lower when the device is on (it's a MOSFET so it conducts in both directions), so it's probably not as bad as it seems, the MOSFETs are always on when the diode is supposed to conduct current. Even in the worst case, this is not catastrophic, but it will lead to some higher losses which could be reduced with an additional parallel diode.
If you already have some SiC MOSFETs, it would be very interesting to check this. If you put some reverse current through the MOSFET with a current limited supply, you can measure the voltage drop across it with Vgs = 0 and Vgs = 15 V . If it's lower with a high gate voltage, there shouldn't be any problems.
Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
Careful with the SiC and no negative gate bias. You will likely incur high switching loss due to dv/dt induced gate turn on of the device that should be off, causing a brief cross conduction. Speaking from experience with that exact SiC FET, and the same gate drivers, i found a -4V bias to be sufficient for inductive switching.
(Sorry for double post, couldn't figure out how to attach a pic with edit.)
Here is how i put a negative bias on my gates with these gate driver ICs (applying nearly the maximum 24V to them). The gate-emitter(source) connects to the 2 pin connectors (G1/G2). The resistors (10K) can be changed to achieve different bias points, for example 10K and 2.2K would be better for SiC as it prefers a high gate voltage and doesn't need too much negative bias.
I've hacked this circuit into boards when I discovered dv/dt induced gate turn on was a problem for my design, especially with fast switching fets.
Registered Member #72
Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659
Steve Ward wrote ...
(Sorry for double post, couldn't figure out how to attach a pic with edit.)
It's a bit of a rigmaroll, but, post the pic in the attachments thread, edit that post to access the link to the picture, copy it, then edit your original post and paste the link in.
Registered Member #4465
Joined: Wed Apr 18 2012, 08:37AM
Location: Bucharest, Romania
Posts: 145
@Steve Ward That was a very good suggestion, thank you for your input. This information is important to the design of optimized gate driver for SiC-MOSFETs, in order to drive SiC MOSFETs in such a way as to facilitate lowest possible conduction and switching losses.
Registered Member #4465
Joined: Wed Apr 18 2012, 08:37AM
Location: Bucharest, Romania
Posts: 145
A new batch has just arrived from the PCB manufacturer for me to test. I need to find a way to use negative gate bias as per Steve Ward’s suggestion.
Registered Member #4465
Joined: Wed Apr 18 2012, 08:37AM
Location: Bucharest, Romania
Posts: 145
Up to this moment I didn’t have all the components required in order to start testing, but I have prepared a modified PCB version to include some stand alone DC-DC converters needed to implement the virtual ground. I was considering using -5VDC_DC converters for the SiC MOSFET and -9V/-12V for the standard MOSFETs. The new PCB:
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