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mister_rf

Tue May 12 2015, 07:18PM

Registered Member #4465 Joined: Wed Apr 18 2012, 08:37AM
Location: Bucharest, Romania
Posts: 145

Very professional job done here. I like to learn from your experience. I already adapted my own project to include the pulse skipping concept.

Wolfram

Wed May 13 2015, 02:00PM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

mister_rf wrote ...

Very professional job done here. I like to learn from your experience. I already adapted my own project to include the pulse skipping concept.

Thanks. I'm sure you will like it, it can be a bit tricky to get all the phasing and timing right, and bus feedback is essential when running from unsmoothed mains, but the high efficiency and clean switching is definitely worth it.

The first revision of the prototype boards arrived yesterday, and I hope to put one together within the next few days, if time allows. 10 boards at a cost of 25 dollars including shipping is not bad at all, and makes it easy to do prototypes on PCB.

I'm doing some changes to the 4 layer board as well, so that the IGBTs and rectifier can be mounted on the underside of the board. This allows for easier mechanical mounting.

mister_rf

Thu May 14 2015, 04:32PM

Registered Member #4465 Joined: Wed Apr 18 2012, 08:37AM
Location: Bucharest, Romania
Posts: 145

I had been snooping at your project, and thereâ€™s something Iâ€™m not sure about.

Are you using the 74109 series on IC2 also? There are some â€œstrangeâ€ connections regarding that circuit.

Wolfram

Thu May 14 2015, 05:14PM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

You're correct that it's a 74109, it's the loop divider for the PLL. Running the PLL at 2x Fres makes it easy to digitally phase shift the feedback signal by 90 degrees, to compensate for the 90 degree phase shift of the XOR phase detector, so that current feedback can be used. The circuit is taken from Conner's DRSSTC controller.

Earlier I used tank capacitor feedback, which was naturally 90 degrees shifted from the inverter current, but I already needed a current transformer on the bridge output for inverter protection, and adding a single 74HC109 allowed me to use this for feedback as well. This has the added benefit of galvanic isolation, so that I can use the driver with non-isolated LCLR as well. Note that for LCLR, the current feedback can not be taken from the inverter output (the phase angle is not monotonic below resonance), so the CT needs to be fed from a sample of the tank current, which can be done easily by sensing the current through a small capacitor in parallel with the tank. This will sacrifice inverter overcurrent protection, but LCLR is inherently immune to work coil shorts so that's not a big problem.

I've attached the schematic, and feel free to IM me anybody who wants the raw eagle files. Keep in mind that this is a revision that's not yet tested so there might be errors. I haven't cleaned up the schematic so it's a bit messy and some component values are wrong, but it is more useful than reading the circuit from the board.

Edit: the file attachment function isn't working right now so I uploaded the schematic to my dropbox:

mister_rf

Thu May 14 2015, 06:24PM

Registered Member #4465 Joined: Wed Apr 18 2012, 08:37AM
Location: Bucharest, Romania
Posts: 145

let's see if my initial guess about your schematic was close to the original...

1431627842 4465 FT1630 Pll Driver Circuit X

Later edit

Well, maybe I have missed something, but in my opinion I have spotted an error there.
The asynchronous reset-direct input Rd and the asynchronous set-direct input Sd are both active low inputs, and the L&L combination must be avoided. Am I right?

Wolfram

Thu May 14 2015, 07:53PM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

mister_rf wrote ...

let's see if my initial guess about your schematic was close to the original...

Wow, that's very close, impressive work. I could have given you the schematic if you had asked, but I guess you are like me and enjoy some nice reverse engineering work :)

That's a nice catch, you're completely correct. I've apparently done this mistake several places, where I've grounded the asynchronous SR inputs on the flip flops wher they are not used. I'm too used to flipflops with non-inverting SR inputs so I connected them to ground without even thinking about it. You saved me significant troubleshooting time and confusion there, thanks a lot. I will fix it right away.

Edit: I've fixed it now, and the updated schematic is here:

. Please tell me if you notice anything else that seems wrong. I've quickly gone over all the logic polarities and I didn't see anything else obviously wrong.

Wolfram

Tue Jun 16 2015, 08:07PM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

It's been a while since I updated this thread. The project hasn't been inactive though, it's just hard to find time to sit down and document it these days.

A lot has happened in the meantime. I received the prototype boards a few weeks after ordering them, and managed to put one together. Some bodges with magnet wire were needed, as the boards were submitted to production before mister_rf found my flip-flop wiring bug. Everything works correctly, including the pulse density modulation and overcurrent detection, but there are still some things I want to improve. There are mainly two issues which i'll describe here.

The first issue is that the PLL easily loses lock. Especially at low bus voltage, low pulse density settings and when the PLL is set to switch early. This was never a problem in my first prototype that used capacitor voltage feedback, so it must be fixable. I did some modifications that improved the situation, but it still loses lock under some conditions so I'm working through the circuit step by step to make it more stable. The main modification that helped was to limit the upper and lower frequency of the PLL. The lower frequency can easily be changed with the resistor connected to pin 12 of the 4046, and the upper frequency can be limited by a voltage divider between the loop filter and the VCO input. Limiting the minimum power setting also helps. I'm slowly working through the circuit, using the totally stable prototype 1 as a comparison.

The second problem is more subtle and more fundamental. It's not really a big problem, so I didn't notice it until now, but I still want to fix it. The symptom is that the switching phase angle changes with the pulse density setting. The change is not huge, and the target phase can be set so that soft switching is maintained down to some reasonably low pulse density setting. The reason for the problem was a bit more mysterious, but again Steve Conner gave me some ideas. The fundamental problem is that the PLL loop dynamics change when pulses are skipped. During this idle time, the PLL is sensing tank current but not controlling it. For my circuit to work properly, the PLL loop needs to be stable both when the loop is open and closed. I've only designed the loop filter for stability when running closed loop. Indeed, the integrator loop filter will be unstable when running open loop, and the frequency drifts during the idle time. Now I need to figure out a loop filter to make it stable in both conditions. Most likely, this will only need an extra resistor and maybe a cap, but I haven't dug that deep into the theory yet. Hopefully, fixing this problem will also help with the first problem.

The values that need tweaking in my schematic are the following: The low pass filter for the bus voltage sensing needs to suppress switching noise but still be fast enough to stabilise the bus voltage. I ended up using 10k/100p , but even more capacitance could help when using lower switching frequencies. The dead-time should be set for a few hundred nanoseconds as a starting point. Target phase needs to be tweaked until it locks and then for ZVS and/or ZCS.

Wolfram

Mon Jul 13 2015, 04:17PM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

I've now figured out both problems from the previous post.

Part of the lock problem was caused by strange behavior of the 74HC4046 VCO outside of the recommended input voltage range. The TI datasheet recommends staying between 1 and 4 V for VCOin. My circuit does not have a restriction on the VCO input voltage, so it can potentially be between 0 and 5 V. The chip I used for the first prototype behaved nicely from 0 to 5 V, but for the second prototype I used a 74HC4046 from TI, which does some very strange things. Below 0.8 V in, the frequency steps abruptly to half of the value, and any further lowering of the control voltage has no effect at all. Increasing the control voltage above 4 V leads to an exponential rise in the output frequency until it hits 10 + MHz at 5V (with a 1 nF timing cap). Needless to say, this does some strange things to the loop dynamics, and the thing was hard to get stable, especially when the resonance frequency ends up in the middle of the step around 0.8 V. I added a resistor network, with 12k to VCC, 12k to GND and 6k8 to the loop filter output, all connected to VCOin. This made it behave a lot better.

I was still not entirely happy with the PLL current feedback. It's hard to get nice feedback with low phase shift when far from the resonant frequency. I experimented a bit more with capacitor voltage feedback, and it's a lot easier to get working well. Since I want to use capacitor voltage sensing for capacitor protection, there's no disadvantage to changing back to capacitor voltage feedback. After playing a bit with LTSpice, I managed to make a nice network for measuring average cap voltage and phase, without introducing unreasonable phase shifts or zero crossing asymmetry over a wide range of voltages and frequencies.

1436804225 33 FT168388 Ih Pll Input Stage

The second problem turned out to not be a problem at all. The switching phase angle appeared to change when the pulse density was adjusted, but this was not what was actually happening. As I was adjusting the pulse density, the primary current changed, and since this current is what commutates the midpoint voltage, it appeared the same way as adjusting the switching phase angle. Now that I understand it, I don't worry about it. Even if adjusted for perfect ZVS at maximum power only, the lower conduction losses will compensate for the increased switching losses at lower pulse densities. It's also possible to inject the sensed primary current into the phase setpoint to compensate, but I don't think it's worth the effort for a marginal increase in efficiency.

Feeling relatively comfortable about the design, I finalized my four layer board and ordered boards. There have been significant changes since the last screenshots I posted. The FR4 thickness between layers 1/2 and 3/4 is significantly thinner than between 2/3, so I moved around some layers to minimize bridge midpoint capacitance. I've moved the IGBTs and changed how they will be mounted. Some hold-down brackets will be glued to the bottom of the PCB, and these will clamp the IGBTs to the heatsink with even pressure over the die. Whether this is practical remains to be seen.

To modify my previous design to work like the latest version only needs some minor mods. I can try to draw up a schematic of what to do in the near future.

Mads Barnkob

Thu Jul 16 2015, 07:14PM

Registered Member #1403 Joined: Tue Mar 18 2008, 06:05PM
Location: Denmark, Odense C
Posts: 1968

You are really pushing this nice project to a professional level now :)

This is kind of a specific question to your circuit, I see that you used the ACS758 hall current sensor.

How satisfied are you with its performance?

From the datasheet it looks like a versatile CT replacement for many types of power circuits used in 4hv projects.

4us response time, not sure if that is fast enough for high current drsstc applications, but its 1 second 1% duty cycle rating of 1200A is rather amazing, it is only limited by die temperature, so some large water cooled busbars or flat large area copper clad with air cooling could properly push it further :)

Wolfram

Fri Jul 17 2015, 12:03PM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

Thanks

The current transducer was added after my present prototype, so I haven't tested it for this project yet, but I've tested the very similar ACS710 in a different project

.

These hall effect sensors are less accurate than regular current transformers and the much nicer closed-loop LEM DCCTs, but if you can live with a few percent error, they are very nice. The bandwidth is also a bit limited, so I wouldn't use them for TC current feedback at 150 kHz for example.

Also note that these sensors are ratiometric, so the output voltage is a product of the supply voltage and the sensed current.

I do have some experience with using these kinds of sensors for extreme peak currents. We managed to magnetize (basically giving an offset) both these and the LEM ones with around a kiloamp, but this was with a unipolar pulse and the typical DRSSTC waveform would probably "degauss" them quite well due to the bipolar nature and the ramp down in current. We were limited to using low current sensors, as we wanted to measure the ~ 9 A nominal klystron cathode current accurately, I suspect a 100 A sensor would be more robust.

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Moderator(s): Chris Russell, Noelle, Alex, Tesladownunder, Dave Marshall, Dave Billington, Bjørn, Steve Conner, Wolfram, Kizmo, Mads Barnkob