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Registered Member #2310
Joined: Wed Aug 19 2009, 08:04PM
Location: Santa Catarina - Brazil
Posts: 169
Hello Wolfram!
My Tank caps are 48x 110nF - 630v MKPs My workcoil is about 0.8uH (so 77,8Khz)
And I have no idea of what's the material of the cores, since I extracted them from a SEW Eurodrive 3-phase filter used probably on industrial inverters.
The other options that I have In hands are those Yellow and white cores from ATX supplys, that are bad I think...
But... I have some nice and big ferrite E-cores, so for me is much easier building an LCLR IH...
Registered Member #3379
Joined: Mon Nov 01 2010, 06:34AM
Location: Sydney, Australia
Posts: 24
Hi Wolfram, I like your method of power control by pulse skipping and have read your link to the pulse skipping article but I am having trouble understanding it. I have built a series resonant induction heater and would like to implement this form of power control. I have been bench testing a jk flip flop but I can see that it skips only every second cycle once the comparator reaches its threshold. Is this correct? I am using a halfbridge. Is it possible to implement pulse skipping with a halfbridge as I noticed that you are using a fullbridge. Thankyou. Claude.
Registered Member #33
Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971
Claude wrote ...
Hi Wolfram, I like your method of power control by pulse skipping and have read your link to the pulse skipping article but I am having trouble understanding it. I have built a series resonant induction heater and would like to implement this form of power control. I have been bench testing a jk flip flop but I can see that it skips only every second cycle once the comparator reaches its threshold. Is this correct? I am using a halfbridge. Is it possible to implement pulse skipping with a halfbridge as I noticed that you are using a fullbridge. Thankyou. Claude.
Hey Claude. The method isn't new, but I've only seen a few people here use it, most notably Steve Conner in his PLL DRSSTC driver. In the litterature it is often called Pulse Density Modulation (PDM), so if you want to find more info this is a good name to search for.
The method is pretty simple. In my implementation, I use the sensed voltage from the tank cap to control the skipping. Whenever the capacitor voltage is higher than the reference, the bridge outputs are disabled. The number of cycles that will be skipped depends on the reference and how much load is placed in the heater. You need to make sure that it skips an even number of cycles so that you have the same number of positive and negative cycles. If you clock the JK flip flop from the same signal that controls the bridge, it will always skip an even number of cycles.
You also need to make sure that the phasing between the sense signal (tank voltage or current) is matched to when you need the signal. The tank voltage is shifted 90 degrees in relation to the bridge output voltage. The JK flip flop samples on the rising edge of one of the bridge outputs, so exactly when the cap voltage peaks. This means you can connect your comparator directly to the JK flip flop. I used this method originally, but there is some risk of metastability if the flip flop is clocked exactly when the comparator output changes state, so I went to a different method.
If you use tank or inverter current for feedback, the bridge output switching matches with the inverter/tank current zero crossing, so you need a second flip flop to hold the comparator state until the "Enable" flip flop can sample it. This method can also be used with tank voltage sensing, and it will solve the metastability problem. This is what I'm doing now, and you can see it in my latest schematic.
If you have little smoothing on the DC bus, it is important that you get the comparator reference voltage from the DC bus voltage. This will ensure that the circuit will be stable, and it will also ensure good power factor. If you have large electrolytics across the DC bus, it is not that critical, but still a very good idea.
For skipping pulses, I turn on both bottom switches to short out the tank circuit. This traps energy in the tank. This is not possible to do with a half-bridge, but you can open both switches to recycle the energy back to the DC bus, and it will still work fine. This is what Steve Conner does in his PLL DRSSTC driver.
What is your circuit like now? Do you have a schematic?
The other options that I have In hands are those Yellow and white cores from ATX supplys, that are bad I think...
Right, these are no good here. The yellow/white ones are iron powder. These are very lossy for HF transformers, and the permeability is low so magnetizing current will also be high. Ferrite is the only good alternative at these frequencies. I looked a bit into using RF type iron powder cores (Micrometals type 2) for the matching inductor in an LCLR heater, but they are simply too lossy at reasonable flux densities. Ferrite and air core are the only options that seem realistic.
As a final note, I want to try a transformer coupled LCLR where the matching inductor is designed as leakage inductance in the isolating transformer, just like the current limiting shunts in neon sign transformers and microwave oven transformers.
Registered Member #3379
Joined: Mon Nov 01 2010, 06:34AM
Location: Sydney, Australia
Posts: 24
Hi Wolfram, thankyou for the excellent explanation of your method of pulse skipping. I am able to understand it much better. My circuit is similar to Uzzors pll series induction heater(I am unable to post a link)except that I don't have the tank overvoltage protection and I use the UCC driver ic's with a gate drive transformer. I like those Silabs drivers that you have. It works well at low power but I have not tried it on a high power level, that's why I would like to try pulse skipping. I will keep you updated. Claude.
Registered Member #3379
Joined: Mon Nov 01 2010, 06:34AM
Location: Sydney, Australia
Posts: 24
Hi Wolfram,I have been working on the pulse skipping circuit but having some problems. It is similar to yours except that the reference for the comparator is taken from the +15v supply. I am using cmos logic and I have 1500uf of bus capacitance. Operating frequency is 80Khz. The pulse skipping works reasonably well until it tries to skip too many pulses and then the comparator output seems to latch, outputting pulses the same frequency as resonance therefore acting as if there was no pulse skipping or current limit. This is noticeable if the workpiece is removed slowly from the coil. It will skip pulses up to when the piece is about halfway out and if it is removed any further it will latch on fully. I have tried two different comparators with the same result, LM319 and LM393. What comparator are you using? Do you use the Set & Reset from the same flip flop as the clock input or is it a seperate flip flop? I have tried both and the one from the same flip flop works best. I noticed in your last video that you showed a pulse skip trigger. Is this the comparator output? I am thinking that the problem might be with the reference for the comparator, but I remember you saying that if there is a lot of bus capacitance is is not critical. Claude.
Registered Member #33
Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971
Hey Claude.
So if I understand right, when you place a load in the coil and remove it, at some point it will latch on and current draw will go way up? Some comparators can have unexpected behavior when either input goes beyond the acceptable range, especially with these old comparators. Are you running the comparator from +15V and GND? Can you draw a schematic of your current implementation with the flipflops and provide some oscilloscpe pictures? There are many ways to do the relative phasing between the tank circuit voltage and the logic, and this can lead to some confusing problems.
I'm using some obsolete comparator I found, I'm out travelling for the weekend so I can't check the part number, but I think it was the CMP-01. It's not ideal but it was the best I had at hand. I've ordered PCBs for the next revision of the prototype, and for this I will use the MCP6562 which is superior in every respect and very cheap.
Currently my flipflops are connected like in the last schematic I posted, I can doublecheck when I get home on Sunday. It took some time to figure out the right phasing between the PLL and the pulse skipping.
The pulse skip trigger (blue trace) in my video is the comparator output yeah.
As you mentioned, I had some instability when using a DC reference for the comparator, but not when I had an electrolytic (470 µF) across the DC bus. This is only a problem when running with little bus capacitance. If you run into this problem, it will look like oscillations on the DC bus and potentially some awful noises.
Registered Member #3379
Joined: Mon Nov 01 2010, 06:34AM
Location: Sydney, Australia
Posts: 24
Hi Wolfram, I have posted my schematic and some scope shots. First scope shot, upper trace is disable pulse from flipflop. Disable pulse must go low to disable driver chips. Lower trace is inverter current. Second scope shot, more pulses skipped. Upper trace disable pulse. Lower trace is inverter current. Third scope shot, upper trace is disable pulse. Lower trace is output from comparator. Fourth scope shot, upper trace is inverter output. Lower trace is inverter current. Sorry for the quality of the pictures. I have noticed that when I increase power with the variac it starts skipping pulses and the inverter positive output stops rising but inverter negative voltage swing keeps increasing until it no longer skips pulses and inverter current rises out of control. Claude.
Registered Member #33
Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971
Thanks for the schematic and scope shots, that makes it clearer.
I think there are a couple of problems with the circuit. The reset signal for the 4027 comes from an inverter from the clock to the 4027. The 4027 samples on the rising edge, and when this happens the reset will still be high due to the propagation delay of the inverter. Since the reset is high when the clock rises, the clock doesn't do anything and you essentially have an RS-flip-flop. The pulse-skipping will not be synchronized to the bridge switching, but due to the 90 degree shift between the bridge voltage (fundamental) and the capacitor voltage it will be close to the current zero crossing. It would not be so bad if the phase shift was always known to be exactly 90 degrees, but you don't know that because of your loop filter. The PLL loop filter is not ideal, the loop time constant and loop gain are set by the same control, and the phase shift will depend on where in the lock range the PLL is running. These things together could lead to some interesting interactions between the PLL and pulse skip circuit. Your circuit could easily be changed to be identical to my first one, which should be immune to these problems.
I'm not sure if this is the reason for your trouble. It could also be something else. When you run the pulse skip setpoint from a fixed DC voltage, the circuit will always try to maintain a given tank voltage. This also means that the input power is a fixed value, and if the input voltage decreases then the current needs to increase to maintain the power. If the supply impedance is relatively high, it could happen that as the voltage dips, the current needed to maintain the power makes the voltage sink even more, which leads to increased current again, essentially forming a positive feedback loop. This is a problem with any regulated supply and power converter. If this happens, you will see the input current skyrocket, the input voltage fall, and the tank voltage (and current) stay constant.
Registered Member #3379
Joined: Mon Nov 01 2010, 06:34AM
Location: Sydney, Australia
Posts: 24
hello Wolfram, I think I have solved part of my problem but created another. Looking at my first schematic, when the pulse from the pll goes from high to low it is inverted and puts the reset high.This resets the flipflop causing only half the cycle to be skipped. This is why the negative portion of the bridge voltage kept increasing. I have now simplified my circuit by replacing one of the drivers with a non-inverting one. This allows me to remove the inverter logic and use the same disable pulse to reset the flipflop. The disable pulse must go low to disable the driver ic's. This now allows complete cycles to be skipped. I have tested it at low power and it works well. I can even remove the workpiece and more cycles will skip and inverter current will stay at the set level. The problem which I have now is that sometimes when I apply power to the control circuit the Q output from the A flipflop will not go high to enable the driver ic's. Not sure if it is a timing problem as it happens randomly. I would to try to take the reference for the comparator from the buss voltage as you did to see if it makes a difference but I am a bit concerned about connecting the negative of the buss to the negative of the low voltage 15V supply. I read your explanation of the phase locking network. I don't seem to have noticed any problems with mine. It keeps a tight lock on the phase relationship even when I place different sizes of metals in the coil. I would like to ask you, should the output of the comparator be in phase with the top of the sinewave of the capacitor voltage. I have noticed that the comparator output slightly lags the capacitor voltage. Claude.
Registered Member #33
Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971
That looks better, but there's still something which bothers me a bit. You've connected together J and K. Q will toggle when both are high, and remain the same when both are low. This means that after it skips a pulse, it could potentially stay disabled, and if two subsequent pulses need to be skipped, it would be re-enabled on the next cycle. To get the proper function, you should invert the K signal going into the JK flip-flop (in effect making it a D flip flop).
For your second question, the output of the comparator should be high whenever the tank capacitor voltage (divided down) is higher than the setpoint voltage for the comparator, plus any delay from the comparator itself.
There have been some updates on the project. The prototype was getting a bit complex, so I designed and ordered a board for it. With the newest changes, it's a bit closer to Steve Conner's DRSSTC driver. Now I take PLL feedback from the tank current intstead of the voltage. As the current should be in phase with the bridge voltage, I needed to cancel out the 90 degree shift from the XOR phase comparator. I used Steve's trick here, where I make the PLL run at 2x Fres by placing a divider in the feedback loop, and use a divider with an inverted clock to get back to Fres with an added 90 degree phase shift. This adds up to a 180 degree phase shift, which can easily be cancelled by inverting the signal.
The boards I designed 2 layers, and they include the latest feedback, bus voltage sensing and additional protection circuits. If everything works as expected, I already have a 4 layer design with more improvements ready to go to production. The 4-layer design should provide much better current handling for the bridge, and better signal integrity as well. The board is designed to have all the essential functions on-board, including the power supply. The only thing needed to make them run is to connect a potentiometer for power control and a few buttons and LEDs for start/stop and status. The control port also includes other signals like tank and mains current sensing, mains voltage sensing, VCO frequency and others, so that a more elaborate control panel can be made at a later point. All protection functions are inherent, so it will run safely with the minimal control interface.
As for the coupling transformer, I did some reading and simulations on the proximity effect, and it turns out that using conductors thicker than a fraction of the skin depth will radically increase the effective AC resistance, by as much as a factor of 100. Skin effect tells us that there's little benefit from any conductor over a given size (aside from increased surface area and thermal mass), but I didn't expect a too large conductor to make things that much worse. I did some simulations in Matlab, the following plot shows the effective AC resistance of a 20 layer foil primary as a function of the foil thickness. The green line is the DC resistance and the blue line is the AC ressitance at 300kHz. Notice how it goes up drastically beyond the ideal thickness. Luckily, the ideal thickness is the same as the thickness of regular copper tape.
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Adventures in induction heating
