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High Voltage Planar Ferrite transformers. ( Intial Experiments )

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Patrick

Wed Oct 22 2014, 07:20PM

Registered Member #2431 Joined: Tue Oct 13 2009, 09:47PM
Location: Chico, CA. USA
Posts: 5639

Uspring wrote ...

If that's secondary voltage you are looking at, primary voltage probably looks quite like it.

When you apply a positive voltage pulse to the primary, the current will rise until the pulse ends. Then the current will stay on and drive your input negative. If you don't clamp it, voltage will go to a value where something gives and will clamp it.

The secondary will just reflect this behaviour, i.e. first a positive pulse with the width of the input pulse and then a negative one.

ok but i get the negative pulse first, then the a positive one. and yes the primary and secondary waveforms are exactly the same but transformed by the turns ratio.

So your suggesting the MOSFET diode is clamping the negative dip? (but will evetually get killed no doubt, this would explain excess heat too.)

but what do other SMPS makers do to get rid of this problem?

Electra

Wed Oct 22 2014, 09:52PM

Registered Member #816 Joined: Sun Jun 03 2007, 07:29PM
Location:
Posts: 156

Add another one turn winding tightly coupled to the primary, but opposite phase (got this image off Google to show what I mean) it's often used in forward converters. The diode returns the energy to the supply. It should be a schottky or fast diode I think.

1414014610 816 FT165654 Spill Over Winding

Patrick

Wed Oct 22 2014, 10:47PM

Registered Member #2431 Joined: Tue Oct 13 2009, 09:47PM
Location: Chico, CA. USA
Posts: 5639

Electra wrote ...

Add another one turn winding tightly coupled to the primary, but opposite phase (got this image off Google to show what I mean) it's often used in forward converters. The diode returns the energy to the supply. It should be a schottky or fast diode I think.

Yes i've seen this too. maybe ill have to retry with this solution. My ultimate goal is a push-pull driven planar core bank of transformers. this was just a uni-polar prototype to shake out the issues with fractional or now distributed primaries.

I dont see oscillograms of these negative dips in push-pull circuits though...

Patrick

Thu Oct 23 2014, 05:15AM

Registered Member #2431 Joined: Tue Oct 13 2009, 09:47PM
Location: Chico, CA. USA
Posts: 5639

Im going to make a differetntial measurement, to see what the real waveform is from terminal to terminal across the primary.

Uspring

Thu Oct 23 2014, 10:34AM

Registered Member #3988 Joined: Thu Jul 07 2011, 03:25PM
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ok but i get the negative pulse first, then the a positive one. and yes the primary and secondary waveforms are exactly the same but transformed by the turns ratio.

Swap the leads of your secondary and you'll get a positive pulse first

So your suggesting the MOSFET diode is clamping the negative dip? (but will evetually get killed no doubt, this would explain excess heat too.)

You have a reverse diode in the FET? If you get a lot of (forward) voltage across it, I'm surprised, that it hasn't blown immediately.

Patrick

Thu Oct 23 2014, 03:32PM

Registered Member #2431 Joined: Tue Oct 13 2009, 09:47PM
Location: Chico, CA. USA
Posts: 5639

Uspring wrote ...

ok but i get the negative pulse first, then the a positive one. and yes the primary and secondary waveforms are exactly the same but transformed by the turns ratio.

Swap the leads of your secondary and you'll get a positive pulse first

So your suggesting the MOSFET diode is clamping the negative dip? (but will evetually get killed no doubt, this would explain excess heat too.)

You have a reverse diode in the FET? If you get a lot of (forward) voltage across it, I'm surprised, that it hasn't blown immediately.

but if i change the leads, i think ill blow the ground loop. [laptop:PS:Board] all on the same ground potential.

Diode.

Patrick

Fri Oct 24 2014, 05:51AM

Registered Member #2431 Joined: Tue Oct 13 2009, 09:47PM
Location: Chico, CA. USA
Posts: 5639

I dont get a diferent result even using a battery and isolated (but still grounded to the battery) USB/laptop.
That means the negative dip is real and not a fictitious artifact.

It turns out i blew the MOSFET and gate drive IC. in last nights run. this nights run i blew another MOSFET, but the driver is OK. I dont have many drivers left, and cant run more tests till i get someones better idea of whats going on, instead of my random guessing and poking around.

I dont know what to do...

EDIT 1: this pantent seems to show a similar primary voltage waveform, inverted, as uspring said.

EDIT 2: Crazy though, crazy thought... what if my incomplete plans for a push-pull circuit are suffering from, the missing half of the primary. Perhaps the opposite side of the energized primary serves the purpose of the forward converters' diode and tertiary winding?

Uspring

Fri Oct 24 2014, 10:17AM

Registered Member #3988 Joined: Thu Jul 07 2011, 03:25PM
Location:
Posts: 711

I should habe looked at the circuit you posted initially. When the fet starts conducting it will cause a current rise in the primary, which causes the negative pulse in the secondary. When it stops conducting, the primary inductance will cause a positive voltage jump until the zener conducts. That causes the positive secondary pulse. That is similar to a flyback operation. The zener will have to take all the power of the pulse, which might cause it to blow. If it blows, there is nothing to prevent a huge voltage rise, which might blow the fet.

I'd connect a diode from the power supply rail to the drain of the fet, so that it becomes conducting, when the drain voltage is pushed above the power supply voltage. That will feed the energy back into the supply electrolytics. The diode should have a current rating at least of that of the fet.

Probably the whole thing gets better once you implement the other half of the push-pull and the secondary is loaded.

Patrick

Fri Oct 24 2014, 03:45PM

Registered Member #2431 Joined: Tue Oct 13 2009, 09:47PM
Location: Chico, CA. USA
Posts: 5639

Should the diode from Drain to V+ be arranged as in the forward circuit, but with out the tertiary winding?
The method of failure you describe, is what i had suspected, and fits whats been seen and smelled.

EDIT 1 : check my reasoning, with the law of induction, current change is opposed by voltage, so building current could appear as a dip, intrupted current would have the opposite voltage sign? Thus the diode.

EDIT 2 :
Forward converter modified circuit, now seems to be the solution. the external diodes do get hot after 20 seconds, but the MOSFET is cool or cold, which wasn't the case before. so if youll notice from previous posts, those inexplicable high spikes are gone. Only the primary dip is seen in the following, as the primary is temporarily grounded to grab current. it seems 96mA is conducted for each pulse at the secondary through 400 ohm at 38 V.

13.4 volt dip from the conduction of the FET. This pulse looks profoundly different. It also has a deafening HOWL when it runs, much louder than before.

Secondary pulse (loaded 400 ohms), looks real good. 38 volts, and duration is right. Now heres the great part, 38 / 13.4 = 2.8 withch means a 1:3 or 1.1:3 turns ratio, very close to actual and exciting, ill be moving on to two cores and primaries, with a single seconday. The tail edge "bump" looks greatly lengthen, i think due to the RL constant.

1414190197 2431 FT1630 Primary Diode Zoom

Primary pulse showing a zoom in on that little peak or ring, its 1.4 volts by 800nS. not sure if this matters or will disappear with a true push-pull circuit. that little peak or bump might be the diode going out of conduction when the spike is ending.

primary pulse.

Electra

Sat Oct 25 2014, 12:39AM

Registered Member #816 Joined: Sun Jun 03 2007, 07:29PM
Location:
Posts: 156

Ok remember , volts x second product have to be the same for positive and negative. The negative part as you call it, is the on time of the mosfet the rectangular pulse (which comes first). Next you see the tall but narrower positive pulse, which is determined by how fast the flux can decay, so it chooses it own level depending on what's limiting it.

By the looks of your latest scope shots you've clamped this completely with a diode. I guess you are getting away with this because the off time is so long, ordinarily it would cause a d.c bias in the core, but hay if it works.

I agree with Uspring, that the positive spike, combined with the low voltage rating is probably what's killing them Fets.
Yes think you have it right, push pull is in a way like two forward converters in a mirror image of each other operating alternately.

In push pull your mosfets will see 2x Vin, plus maybe a bit of a spike from any leakage inductance on top, I would have thought choosing 60v or more mosfets if you can, would be reasonable.

Have also seen diodes placed in parallel to the mosfets, then these can be 'better' diodes than the internal ones, and take some of the heat dissipation off the mosfets.
Perhaps look at trying to get big variable power supply for testing the scaled up push pull version, so you can turn it down if it gets too hot, too fast.

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