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What is a "low impedance" DRSSTC? More theory

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Dr. Dark Current

Wed Jun 04 2014, 02:34PM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

Steve, yes it does work as a transformer and it does transform the voltage clamp, but most likely only in "DRSSTC" mode. If the voltage on the primary is constant, the current through the tank capacitor is constant, this is where the "voltage to current conversion" happens - on the reactance of the tank cap.

Uspring

Wed Jun 04 2014, 05:27PM

Registered Member #3988 Joined: Thu Jul 07 2011, 03:25PM
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Posts: 711

Dr. DC:
The equation for Qpri is derived under a steady state assumption. It should work better for QCWs than for DRSSTCs.
A hard arc voltage clamp and constant primary current behaviour implies Qpri being proportional to Qsec. This can be accomodated by the equation if we assume (for a dual resonant zcs QCW coil):

a) Qsec >> 1/k, which makes the first term dominant
and
b) f/fsec is constant, which keeps the proportionality constant

If the coil is e.g. run at the lower pole the first term

(Qsec/k^2) * (1 - f^2/fsec^2)^2

simplifies to about Qsec, i.e.

Qpri = Qsec (for large Qsec)

QCWs are run at much less (peak) power than DRSSTCs, so the assumption of a large Qsec might hold. It would be interesting to know typical primary currents and voltages of your QCW and the k to check, whether this makes sense.

Edit:

Also, I like to view the Q as a ratio of tank circuit voltage vs. bridge output voltage (average values). This makes it easy to calculate the coils and peak currents.

Yes, that basically is what Qpri is.

Steve Conner

Mon Jun 16 2014, 02:35PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

I think I derived another interesting relation.

A PLL driven coil is at risk from hard switching, because the PLL loop filter takes a finite time to respond to rapid changes in frequency. This can only be speeded up so far before the filter suffers from excessive ripple.

Let's assume the worst case situation where the resonator is suddenly shorted by a ground strike leaving the PLL no time to do anything at all about it.

From our previous steady state arguments, the counter EMF induced in the primary by the resonator must be (roughly) equal to the output voltage of the bridge. If the resonator is shorted, this counter EMF will disappear almost instantly. The primary current can't change instantaneously because of the inductance of the primary coil, but its rate of change will change, so it will pass through zero at a different time from what the PLL expects based on previous zero crossings.

From (insert bunch of calculus and trig here

) I think it then follows that the worst case hard-switching current you can possibly encounter is equal to Ipk/Qpri.

If this is true then for the usual designs of DRSSTCs, the resulting current should be within the switching SOA of the kinds of IGBTs normally used. The hard switching may cause increased losses but it shouldn't blow anything up instantly due to latchup or transient overvoltage.

Uspring

Tue Jun 17 2014, 10:02AM

Registered Member #3988 Joined: Thu Jul 07 2011, 03:25PM
Location:
Posts: 711

That's complicated stuff. A first thought is to think of an equivalent circuit for the primary tank to have a resistor added, which causes the Qpri. That would then be shorted during a ground strike, causing a voltage jump in the primary. Makes my head smoke to derive a phase jump from that.
Also it might be a too simplistic way of deriving a phase jump, since the secondary-primary current phase relation might also have an impact. The zcs frequency, which is not the same as the primary res frequency, is also dependent on the secondary. You've probably figured all that, I haven't

For a DRSSTC switching by primary current info via CT, that shouldn't be an issue.

Steve Conner

Tue Jun 17 2014, 11:08AM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

Yes, I don't have a formal proof to go in the (insert bunch of calculus) slot yet

But my argument is based on things happening on a time scale of less than 1/2 cycle, so the separate resonant modes and Qs can be ignored as these are steady state things that only make sense in the context of multiple cycles. It basically reduces to a jump in voltage across an inductor.

Antonio

Sat Jun 21 2014, 01:52AM

Registered Member #834 Joined: Tue Jun 12 2007, 10:57PM
Location: Brazil
Posts: 644

I made some calculations here, ignoring losses. If a drsstc has its output short-circuited after some time (with the short-circuit lasting for several cycles), the input current becomes limited only by the primary circuit, with the secondary inductance reflected to it. As the driving frequency is at approximately the resonance frequency of the resulting LC tank (it is exactly this with the Butterworth filter design), the input current goes up with a ramp envelope, starting from its initial value and increasing by the same amount at each cycle. This amount is 4*V*sqrt(Ca/(La(1-k^2))), where V is the peak voltage of the square-wave driver.

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