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Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
The resistors determine the lock range of the PLL.
The GDT is connected right, but the series capacitor on the GDT primary is too small, the resistor is too large, the gates are missing TVS/zeners, the antiparallel diodes for the MOSFETs are useless and the DC blocking cap in series with the primary coil has a too low value for your application. Consider 10 uF.
Registered Member #9252
Joined: Fri Jan 04 2013, 06:27AM
Location: Andromeda
Posts: 253
Is that correct?
Photo shop does wonders.. But how many volts / watts should the zeners be? Don't you see something slightly wrong with the internal schematic? The internal diode?
Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
I would use 18 V TVS diodes (P6KE series) between the gate and source, but two 18 V ~2 W back-to-back zeners will do as well. I would increase the GDT primary capacitor to at least 4.7 uF and leave the resistor out, the resistor is mainly used if there are no individual gate resistors, and those FETs have a large gate capacitance.
The DC blocking capacitor in series with the primary would probably be good with 10 uF total capacitance but more doesn't hurt.
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Joined: Sun Oct 17 2010, 06:57PM
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StormInABottle wrote ...
Is that correct?
Photo shop does wonders.. But how many volts / watts should the zeners be? Don't you see something slightly wrong with the internal schematic? The internal diode?
I can't imagine 20Kw or anything near that going through that coil.
Registered Member #9252
Joined: Fri Jan 04 2013, 06:27AM
Location: Andromeda
Posts: 253
Correct? And is the large gate capacitance a deal breaker? The capacitor on pins 6 & 7 and the resistors on pin 11 and 12 determine the frequency that the coil runs at. The ratio between R1 and 2 determine how far the oscillator can wander. The 10k potentiometer by pin 9 will adjust the voltage bias on the VCO input and alter the frequency,"
What value should the cap on pins 6 and 7 be (Let me guess.. Somewhere near 200nf)? What about the resistors on pin 11 and 12? Where are The projects cost was cut in half when i removed the diodes. Yay. I hate brick diodes
I disagree that you would need more uF than 1 on the GDT... it's literally just to prevent staircase saturation. And you only have 12V applied from the mosfet drivers. Than again having an excess of F is not a BAD thing so go fore it.
Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
If the GDT primary series capacitor is too small, it forms a voltage divider with the charges of all gates. The gate charge of those FETs is 350 nC at 10 V, that approximately means 35 nF "effective" capacitance. So all 4 FETs have 140 nF of capacitance. As you can see, a 1 uF and 140 nF divider will cause a noticeable drop of the gate voltage.
Edit: Where are your bridge decoupling (rf bypass) capacitors?
Dr. DC - I don't want to claim you wrong, but for my own edification I would like to know how you've concluded this. From my studies the transformer isolates the system. I = ( C * V ) / t (C is the gate capacitance) so even with a full bridge topology you only have 2 on at a time you should design with the ringing effect in mind from the current out of the transformer. Also, the OP could do 1:2:2:2:2 with STE70NM60s and bleeder resistors as they have 30V gates and built in zeners to clamp voltage.
Registered Member #9252
Joined: Fri Jan 04 2013, 06:27AM
Location: Andromeda
Posts: 253
Check the GDT And i have no Decoupling caps. Should i put them? Where and what value? Thank you. STE70NM60 could only tolerate 70 amps. And are expensive bricks.
The capacitor on pins 6 & 7 and the resistors on pin 11 and 12 determine the frequency that the coil runs at. The ratio between R1 and 2 determine how far the oscillator can wander. The 10k potentiometer by pin 9 will adjust the voltage bias on the VCO input and alter the frequency,"
What value should the cap on pins 6 and 7 be (Let me guess.. Somewhere near 200nf)? What value should R1 and R2 be for CW operation?
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PLL DRIVER CIRCUIT QUESTIONS *EDIT*
