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Registered Member #103
Joined: Thu Feb 09 2006, 08:16PM
Location: Derby, UK
Posts: 845
I would think using primary feedback in a DRSSTC with phase comparator 2 would be a lot less risky, due to the strong resonance of the primary inductance and capacitance. You're measuring a strong current on something connected to the inverter. Noise pickup/spurious edge pickup can then be eliminated by normal EMC practices, like screening and board layout...
At least I hope the above is true for a DRSSTC as I'm also going to be using phase comparator 2 on mine
I never did find a good solid reliable feedback mechanism for an SSTC. I still have the opinion that every feedback SSTC works by complete fluke Even if you get a good feedback from the secondary base, the coil can shift the phase, or do whatever it feels like such as jump to a harmonic when you adjust the output.
Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
Well, I made a PLL SSTC which worked perfectly, with 4046 PC2 and secondary base feedback. It was connected in the same way as this big TC. I could draw ground arcs few centimeters from the breakout point and it continued to work, there were no knobs, just turn it on and it works. No harmonics because of the limited VCO range.
But I'm really lost as to what to do with this one... It uses almost the same circuit, just the frequency is 3 times lower. In the meantime I tried 2 other IC manufacturers - no difference. I tried modifying the PLL lowpass filter and various noise suppresion circuits on the INput terminal - no difference... The controller is shielded in a metal case and the 4046 supply is decoupled by an LC filter.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
One other observation: The PLL is trying to achieve zero phase shift between the drive voltage and the secondary base current, but if the secondary resonance is damped heavily enough, zero phase shift can't be obtained at any frequency. It follows that the PLL will just stick at one end of its tuning range.
Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
I just tried -40106 Schmitt inverter before the signal input pin - no difference -reversing the GDT and CT phasing, thinking that the interference might come from the bridge - no difference
So far I have tried at least 10 things, and it still behaves EXACTLY the same. It all points to a design fault inside the 4046 IC...
Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
I think I have found the problem by some more measurements. The phase comparator is getting confused. The VCO output leads the signal input by around 60 degrees, and instead of delaying the output by said 60 degrees, the PC is trying to quicken the output by 300 degrees - so it switches its output between H and high-impedance state. But because the VCO is already at its maximum frequency, this doesn't work. Why do I think this - look at the attached scope shots. The Phase Pulses output is exactly the opposite to what it should be according to the data sheet.
So it seems the only fix to this problem is to stop using this phase comparator
Registered Member #1232
Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881
It all points to a design fault inside the 4046 IC...
...or more likely a problem with your circuit design. The 4046 IC has been successfully used to implement phase-locked loops in the electronics industry for donkey's years! If you design something that marginally works with one manufacturer's part and fails completely with another manufacturer, then this should set alarm bells ringing that your circuit might not be operating the chip properly as intended.
The phase comparator is getting confused. The VCO output leads the signal input by around 60 degrees, and instead of delaying the output by said 60 degrees, the PC is trying to quicken the output by 300 degrees - so it switches its output between H and high-impedance state. But because the VCO is already at its maximum frequency, this doesn't work. Why do I think this - look at the attached scope shots. The Phase Pulses output is exactly the opposite to what it should be according to the data sheet.
The type-2 phase comparator is getting confused by HF noise or harmonics present on the signal input. As I said before both inputs need to be perfectly clean square waves with no chattering (bouncing) at the rising and falling edges. Any double edges (or lingering of the input in the "no man's land" between logic '0' and logic '1') will cause the type-2 phase comparator to think that the signal input is higher frequency than the VCO and set the charge-pump to command the VCO to a higher frequency.
If you really think the PLL chip is faulty, why don't you get two good quality adjustable square wave generators and do a bench test. Look at the output of the type-2 phase comparator on an oscilloscope for the following conditions:
1. Reference frequency is higher than Signal frequency (PC2 output permanently low) 2. Reference frequency is lower than Signal frequency (PC2 output permanently high) 3. Frequencies are the same but Reference leads Signal in phase (PC2 output pulsing low) 4. Frequencies are the same but Reference lags Signal in phase (PC2 output pulsing high) 5. Frequencies are the same and signals are almost perfectly in phase (PC2 output tri-stated most of the time)
If you do this with accurately controlled *CLEAN* squarewaves in a workbench test scenario you should be able to tell if your 4046 IC is damaged or has a design flaw.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Yes. The input amplifier on the 4046 only has about 16mV (IIRC) of hysteresis, so it doesn't take much to trigger a double transition. The waveform you showed has slow edges and looks a bit dirty, so I think it could easily do it.
My cure was to use PC1 where the multiple transitions don't matter.
Registered Member #1232
Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881
Yes. The input amplifier on the 4046 only has about 16mV (IIRC) of hysteresis, so it doesn't take much to trigger a double transition. The waveform you showed has slow edges and looks a bit dirty, so I think it could easily do it.
Yes, very small hysteresis and very fast acting. I've even seen the fast-slewing output from the phase-comparator2 itself toggling state capacitively couple a tiny spike onto a slowly changing high-impedance input waveform! This then changes the state of the PC2 output immediately.
It goes something like this:
1. Input A goes high first 2. So the phase comparator output goes high because input B needs to catch up! 3. The toggling of PC2 output impresses a brief pulse through the threshold of the input B 4. Phase comparator 2 sees this rising edge and thinks that input B has now caught up, so tri-states its output immediately! 5. The real rising edge of the input B signal comes along some time later 6. Now phase comparator 2 has seen *TWO* rising edges on input B so it thinks input B frequency is too high! 7. PC2 output now goes low to tell input B to slow down!!! *NOTE* 8. This state persists until the next rising edge on input A
*Note that this final state (between step 7 & 8) is the exact opposite of what it should be to make the lagging input B signal catch up with the leading input A reference. Input B needs to go faster, not slow down.
This isn't speculation or just something that is theoretically possible. I observed it happening with a 4046 PLL IC using PC2 in a practical application. The key to curing it is to keep the rising and falling edges of both signals really fast, really clean, and the source impedance nice and low.
My cure was to use PC1 where the multiple transitions don't matter.
That's what I would recommend too. Use PC1 and phase-shift the current-sense signal by 90degrees by terminating it into a reactive burden. Or alternatievely, phase-shift the VCO output by 90 degrees using that trick where you synthesise it at 4x frequency and divide it down into two quadrature "gray code" outputs.
PC1 does only give you a guaranteed 90 degree phase at the mid-point of the frequency locking range though. So the phase will vary across the full locking range though.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
PC2 is really a switched-mode integrator because its tri-state output allows the capacitor to hold its charge. This makes the loop second-order, giving 0 degrees phase offset throughout the lock range.
You can achieve the same thing by replacing PC1's loop filter with an op-amp integrator. You get a constant 90 degrees phase offset throughout the lock range. This is how my Mk2 PLL drivers worked. I got rid of the 90 degree phase shift by running the VCO at twice the output frequency and dividing it down in quadrature with a couple of flip-flops.
A second-order loop has some quite unpleasant implications for stability of a regular PLL that has to lock to an independent oscillator. But in the Tesla coil application, the PLL is locking to a phase-shifted version of its own output. This means the loop is really only about 1.5 orders so the stability problems are greatly eased.
Technically the loop is still second-order because the Tesla resonator can introduce a 90 degree phase lag at high frequencies. But this is still much less of a problem than the process of locking two independent oscillators, which behaves like an integrator and adds a 90 degree lag at all frequencies.
Registered Member #1232
Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881
Hi Steve,
Thanks for that explanation. I remember chatting about this some time ago and you had eluded to the fact that the PLL design requirements to properly track the resonant frequency of a TC were in contradiction to what you would normally do to implement clock recovery or motor speed control by PLL.
Now it's clear why. The VCO in a clock recovery PLL (or motor in a speed control application) acts like an integrator itself, because you feed it a voltage, to get a frequency (or speed) but what you are measuring and attempting to control is it's phase (or position.) Hence the integration because phase or position is the time integral of frequency or speed.
So for a conventional PLL the whole loop will be second order because of one pole from the loop filter and one from the integrator action of the VCO or motor. But for a TC you don't get that pole from the plant because the output frequency *HAS* to be the same as the drive frequency. Therefore you can increase the order of the overall loop to minimise steady-state error by going to PC2 that has integrator action built in.
Cheers,
-Richie,
PS. I had a student last year trying to make a modern recreation of a Baird Televisor who had trouble locking the speed of a permanent magnet DC motor to the sync pulses of the incoming video. She has a lot of trouble with motor noise on the PLL input from an IR light-gate, causing the PC2 to act up. If someone chooses the same project again this year I'll get them to try PC1 with an additional integrator to force phase error to zero. Getting loop stability is quite a challange for them though, because of the poles of the loop filter, speed-to-phase conversion, motor L/R, and the inertia of the Nipkow disc! It makes students have to think though!
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PLL SSTC with Type 2 phase comparator problems (added some info)
Even if you get a good feedback from the secondary base, the coil can shift the phase, or do whatever it feels like such as jump to a harmonic when you adjust the output.
