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Registered Member #65
Joined: Thu Feb 09 2006, 06:43AM
Location:
Posts: 1155
@klugesmith At one point, I thought the old Sun Core CPU VHDL mirror from a time before Oracle might be fun to port to a Cyclone IV dev kit. (haha... they no longer even sell this kit... )
* Quickly I discovered the undocumented DDR RAM controller interface lib is locked... so no internal frame buffer for an LVDS LCD... even on the NIOS II uC linux distro they bootstap, you can't change the fact 64MB of ram layout is functionally unmutable. * Downloaded and install Quartus II versions three times (8GB) to find the one that will actually finish an install (web installer failed when I tried it...) * Wizards dominate the workflow, and ultimately make it unusable. * The software framework of NIOS II is not even "beta" quality, and the interesting stuff worth knowing is written in Korean.
People will likely find opencores.org is far easier to grasp even if they choose a Altera chip to start.
Registered Member #3324
Joined: Sun Oct 17 2010, 06:57PM
Location:
Posts: 1276
interesting, il make sure to grap one of the Cyclone's next time i have the funds up again, just building a fullbridge atm, next project will be somthing with FPGAs.. hmm :D
Registered Member #29
Joined: Fri Feb 03 2006, 09:00AM
Location: Hasselt, Belgium
Posts: 500
I come at FPGAs with an eye to using them for real-time signal processing (which they excel at, BTW). I started modestly with a Cyclone II demo board from Terasic
It has flash, SRAM and DRAM and a host of interfaces. In the photo, there is a analog-to-digital converter connected using a ribbon cable (for testing software radio functionality). I went for one of the older FPGAs for reasons of cost and the fact that it was available in a non-BGA format. (I have yet to gain the confidence to solder BGA packages by hand. You really don't want to mess up on a EUR60-100 chip!)
I went on to build my on PCB with two ADCs and two DACs for a software radio transceiver. Filters, DDSs, phase-locked loops, up and downconverting mixers as well as a fast-fourier transform blind carrier frequency acquisition are all implemented inside the FPGA. (This PDF shows the digital PLL lockup transient of the DDS on an incoming carrier.) It is interfaced to a microcontroller that provides a high level user interface and link-level processing.
The QFP package has a very fine pin pitch, so soldering must be done carefully using the solder-flooding/solder removal method, or reflowed using solder paste and a hot-air gun or oven. Be very careful to inspect for short circuits between pins or open circuits from slightly bent pins not contacting the solder pad.
Lots of LEDs of different colors are always important to include in any design!!
Getting to this level took a few months of concerted study. Taking time to learn pays off. The first spin of my PCB worked immediately!
I think hobbyists are scared off by the apparent complexity of FPGAs as well as the costs involved (even smaller FPGAs are significantly more costly than a typical PIC or Atmel microcontroller). What you get in return for your money and effort is a system that can be configured to do just about anything your imagination can cook up and do it very fast! Just take your time to come up to speed on all the pertinent stuff: how the boot process works, how to decouple power supplies, how to preserve signal integrity on you PCB for high-speed digital signals, etc. Above all, have fun learning something new and useful!
Registered Member #65
Joined: Thu Feb 09 2006, 06:43AM
Location:
Posts: 1155
@WaveRider I like the DDS design options, but it has been a tough sell for NI, Analog, and Altera.
A decent DSP demo card is only $50, but they have a few obvious design problems:
This may have changed, but I found most low-level VHDL design liturature is still Xilinx based. ...I too, even considered custom SRAM memory for a brief time....
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