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Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Yeah I agree something like 10-100MSPS is a nice round number, I would have used about that sample rate myself
If you have several samples per period, you can do "Prediktor" phase lead with a simple IIR digital filter, and you can also do the current limit digitally because you have a good chance of capturing the actual peak value.
It also makes life easier if you are sampling fast enough to just drive the gate drivers directly with a 1-bit output. For each sample, you only need to decide if the gate drivers should be off or on. At 1MSPS you would have to synthesize the gate drive waveforms using something like a PWM or timer peripheral clocked off a higher sample rate, and it would degenerate back to being a PLL driver with a digital loop filter. I believe Steve Ward and Phillip Slawinski's latest driver works like this, and it is fine, but full sub-cycle control would be nicer.
Registered Member #2292
Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795
Steve Conner wrote ...
Yeah I agree something like 10-100MSPS is a nice round number, I would have used about that sample rate myself
If you have several samples per period, you can do "Prediktor" phase lead with a simple IIR digital filter, and you can also do the current limit digitally because you have a good chance of capturing the actual peak value.
It also makes life easier if you are sampling fast enough to just drive the gate drivers directly with a 1-bit output. For each sample, you only need to decide if the gate drivers should be off or on. At 1MSPS you would have to synthesize the gate drive waveforms using something like a PWM or timer peripheral clocked off a higher sample rate, and it would degenerate back to being a PLL driver with a digital loop filter. I believe Steve Ward and Phillip Slawinski's latest driver works like this, and it is fine, but full sub-cycle control would be nicer.
Anyway, go Eric!
I'm glad someone can validate my thought process! At least I know I'm not completely off the deep end, yet...
From what I have looked at, my current sample rate gives about 200 samples/period at a 500KHz Fres. I like the idea of being able to just adjust the gate drive output based on the sampled points. That's what originally attracted me to choosing the higher sample rate.
My FPGA can run up to 300MHz and I'm tempted to pick an ADC that can run even faster than 100MSPS. 200 samples/period (10nS resolution) seems like it may be pushing the limits of what should be "enough" samples in a single period. But then again the comparator used in the UD phase lead board is 10nS resolution and runs fine it seems.
I guess the only thing that deters me from going to a faster ADC is that after you go past the 100MSPS mark it seems ADCs go into a whole new ball park of price range! Some even as high as $40 parts for only a marginal improvement in performance.
Registered Member #2922
Joined: Sun Jun 13 2010, 12:08AM
Location:
Posts: 226
Ohh.. I was thinking you want to use it as a 50khz driver hence I said 1MSPs would be fine.
IIR filter you works just fine for the phase-lead compensator, maybe you will have the first cycle not compensated because the capture time for the right initial states on the filter.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
This won't be a problem if you run the ADC and digital filter continuously. The filter will already have the right initial state because it was running before the burst began.
Registered Member #2922
Joined: Sun Jun 13 2010, 12:08AM
Location:
Posts: 226
The filter will almost stabilize to a zero value like the inductor and you will lsot the first prediction cycle. My idea is to pause the filter atualization at the end of the burst
Registered Member #2292
Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795
My plan was not to lead on the rising edge of the first half cycle. You need to create a start pulse to get the current moving in the circuit. However it would only be the very first turn on (when there is zero current) every other transition would run phase lead.
I don't see how you could do phase lead before this time anyway considering the fact that there is no current flowing before this time to lead in the first place.
On top of phase lead however I also have to do all the phase shift modulation and ZVS delay junk as well. It's going to be one busy little FPGA!
I may even consider doing an interleaved ADC design, lord knows I have the pins on the FPGA to do it, but this is yet to be decided.
Registered Member #2922
Joined: Sun Jun 13 2010, 12:08AM
Location:
Posts: 226
Iterleaved ADC will be great. You can try to run a digital based PLL loop to control the output frequency. I think it can regenerate and stabize much faster than a analog simple PLL. This is the hard think on use normal PLL on DRSSTC tesla coils, at QCW system PLL seems to make the job more easy. With the PLL you can make all the lead design, but, I think, you will always miss the first cycle.
If you design a sate machine approach for me it seems simpler to do the phase lead, now you will lost only the first edge, and not all the first cycle.
Registered Member #2694
Joined: Mon Feb 22 2010, 11:52PM
Location: Russia, Volgograd (Stalingrad).
Posts: 97
Eric, why are you change IGBT from IXYN82N120 to TO-247? is this mean IXYN82N120 aren't working because of it is too high frequency for this IGBT or here is a cooling trick?
Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
I think if the phase lead misses a few cycles, it is no deal, especially in a QCW coil where the current takes many cycles to ring up. The phase lead is important during the time when the tank current is near its maximum value.
Registered Member #1749
Joined: Fri Oct 10 2008, 02:04AM
Location: Claremont New Hampshire
Posts: 497
Goodchild wrote ...
As for our water cooling design we know that it's not an "optimal" design, but the fact remains we used materials we have on hand. We also don't plan to run the bridges at any extreme levels so out current design fall into the spec we plan to run at.
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"The HOG" Supersized QCWDRSSTC
Great work!