"The HOG" Supersized QCWDRSSTC / Projects / Forums

Forums

4hv.org :: Forums :: Projects

« Previous topic | Next topic »

"The HOG" Supersized QCWDRSSTC

first previous 3 4 5 6 next

Move Thread

LAN_403

tobias

Wed Nov 21 2012, 01:03AM

Registered Member #1956 Joined: Wed Feb 04 2009, 01:22PM
Location: Jersey City
Posts: 172

I usually group the pieces in subassemblies and then pull only a few lines between them. Depending on the assembly that is not an option though.

Is the assembly so heavy it will just sit flush or do you have some kind of mechanical attachement planned?

Goodchild

Sat Nov 24 2012, 07:38PM

Registered Member #2292 Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795

Main thread updated with parts and water block assemblies.

tobias:
We will have the bridges sitting on two T-slot extruded rails that will be supporting the bridges. It will be attached via 90* brackets that mechanically attach it to the rails.

Goodchild

Fri Dec 28 2012, 08:28AM

Registered Member #2292 Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795

Main thread update with MICA caps and bus caps.

Last update of 2012 wee! The project is entering it's second year now. We started back in late 2011 around this same time.

teravolt

Sat Dec 29 2012, 02:20AM

Registered Member #195 Joined: Fri Feb 17 2006, 08:27PM
Location: Berkeley, ca.
Posts: 1111

if your blocks store to much heat you could hog out the back to increase the water surface area and solder a back plate on

Goodchild

Tue Aug 27 2013, 06:16AM

Registered Member #2292 Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795

UPDATE 8/26/13

Updated original post with new progress.

Chris Cristini

Tue Aug 27 2013, 07:29PM

Registered Member #1749 Joined: Fri Oct 10 2008, 02:04AM
Location: Claremont New Hampshire
Posts: 497

Love the solid works Design and your work reminds me of something a manufacture came up with great standards.

Gregory

Wed Aug 28 2013, 02:40AM

Registered Member #2922 Joined: Sun Jun 13 2010, 12:08AM
Location:
Posts: 226

What IGBT do you plan to use?

I already made some FPGA based phase-shift and it appear to works pretty well.

I used a counter to make the ramp and it was even auto-ajustable to the FB frequency. Something that is not possible with the constant-current source with capacitor with analog ramp generation

Goodchild

Wed Aug 28 2013, 03:47PM

Registered Member #2292 Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795

Gregory wrote ...

What IGBT do you plan to use?

I already made some FPGA based phase-shift and it appear to works pretty well.

I used a counter to make the ramp and it was even auto-ajustable to the FB frequency. Something that is not possible with the constant-current source with capacitor with analog ramp generation

Gregory,

When you did your FPGA design did you use an ADC front end? Or did you use a standard comparator/inductor and phase lead setup like on the UD2 to produce a clock that feeds the FPGA?

I'm curios if you did use an ADC front end how fast of one you used? I have been battling with ADC speed over cost and will probably settle for something in 10-bit 100MSPS range.

I plan to do the phase lead (normally done via an inductor and comparator) all inside of the FPGA. This gets rid of one of the CTs and a bunch of extra hardware on the board. It also builds in much finer control of the primary current, becasue the FPGA gets access to the amplitude information for regulation and current limiting.

Gregory

Thu Aug 29 2013, 02:15AM

Registered Member #2922 Joined: Sun Jun 13 2010, 12:08AM
Location:
Posts: 226

I used the standard inductor with comparator. I think that 100MSPS is actually much more, MUCH more than what you really need. Something around 1MSPS will do the job very well.

I go a little further and say that you can do it with a 8 bit ADC. But, 10 bits will do only better.

I don't know if I like the idea of have a ADC reading a feedback of a tesla coil, but I don't see why it can't work.

My skype is: gregory_gusberti I deleted my facebook.

Goodchild

Thu Aug 29 2013, 07:20AM

Registered Member #2292 Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795

Gregory wrote ...

I used the standard inductor with comparator. I think that 100MSPS is actually much more, MUCH more than what you really need. Something around 1MSPS will do the job very well.

I go a little further and say that you can do it with a 8 bit ADC. But, 10 bits will do only better.

I don't know if I like the idea of have a ADC reading a feedback of a tesla coil, but I don't see why it can't work.

My skype is: gregory_gusberti I deleted my facebook.

It could be done with a 1MSPS ADC I think, however I decided not to for a couple reasons. First by oversampling at 100MSPS I can run the FPGA and ADC from the same clock (100MHz) and do real time computations on the input signal. If I ran at 1MSPS that would be just a little over the first nyquist zone (2*f) and would require that the FPGA do extra math to construct the rest of the sine wave. This is important because the FPGA needs to be able to make changes in the output signal with a resolution of at least 10nS in order to work properly for phase lead at the frequency I'm running.

Gregory, if you ran at 1MSPS how would correct for the fact that you only had two data samples per period?

Lastly at $16 a 100MSPS 10 bit ADC is not that expensive, coupled with an $18 FPGA it ends up being a rather cheap controller with a lot of horse power.

If anyone has experience with DSPs I would love to hear your take on this! I'm new to this kind of advanced DSP and I'm learning as I go.

first previous 3 4 5 6 next

Moderator(s): Chris Russell, Noelle, Alex, Tesladownunder, Dave Marshall, Dave Billington, Bjørn, Steve Conner, Wolfram, Kizmo, Mads Barnkob