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Registered Member #2919
Joined: Fri Jun 11 2010, 06:30PM
Location: Cambridge, MA
Posts: 652
loveHV wrote ...
There are so many variables XD
You can always use a worst-case estimate (no snubber, "reasonable" guess for bus inductance) and proceed from there. It'll tell you whether you're close or catastrophically off.
Registered Member #15
Joined: Thu Feb 02 2006, 01:11PM
Location:
Posts: 3068
dude_500 wrote ...
I strongly disagree that it is almost necessary or that it will probably burn out without laminated DC bus. I would guess that easily much more than 99% of DRSSTC's made do not have laminated DC bus, and work just fine!
Of course, that's not to say that it's not ideal.
I agree. You DO NOT need a fancy laminated bus or even simple copper bus for high current bridges. We design lots of PCB board based bridges for CM300 and CM600 IGBTs in induction heating applications for very large commercial applications and use just simple double-sided, 3 oz. copper boards. If you know the current in your design and the proper pcb design equations for temp rise in copper traces, you properly design a board that meets your requirements without going to more costly copper bus. Plus, you can design a bridge much easier with good coupling between your bus and return to reduce inductance more easily than using copper or laminated busbar.
Registered Member #1854
Joined: Wed Dec 10 2008, 06:09PM
Location: West-Flanders Belgium
Posts: 88
Hi a quick calculation of the spike using the theory of counter voltage created by an inductance.
First how much current may be flowing in such a way i don't exceed my voltage rating of my tank capacitor.
F0 = 120kHz, Ct = 100 nF 6kV
Zt = 1 / (2 * pi * f * C) = 13.26 ohm
Maximum current: 6kV / 13.26 ohm =~ 450A
inductance of the bus:
ESR of aerovox 2200µF capacitor is 44m ohm at 10 kHz
at 10kHz we neglect the effective resistance of the bus cap and we consider the 44m ohm to be pure inductive
So the L value of the buscap is : Lb = (0.044) / (2 * pi * 10k) = 0.7µH. For the Bus planes we take a worstcase value of 0.1µH
So thats 0.8 µH in total
The current changes in a sinusoidal manner. From 0 to 450A we take 1/4 of a waveform (from zero to max).
One full wave takes up (1 / 120kHz) = 8.33µs a quarter is 2.08µs ~
The inductive kick will be as following : Uk = L * (di / dt) = 0.8µ * (450A / 2.08µ) = 173.1V spike.
Worst case calculations and some asumptions, if one of the asumptions is incorrect then the whole calculation is gonna be affected XD so be precise if you see anything wrong with my reasoning.
I know there are parasetic resonances, i ain't taking that into account.
Here is a new concept of the bridge with the bus planes stacked:
it isn't completely finished but it gives an idea :p
Registered Member #15
Joined: Thu Feb 02 2006, 01:11PM
Location:
Posts: 3068
Some comments:
1. You should have a return plane under your gate drive. This is really important as it reduces parasitic inductance in that circuit.
2. Check voltage clearances. Use IPC-2221 as guideline for minimum trace to trace clearance for the voltages needed.
3. Before you do layout of the MOSFETs, build a model for the heatsink arrangement being used. This should be done first and then you can design the board around the heatsink.
Registered Member #1854
Joined: Wed Dec 10 2008, 06:09PM
Location: West-Flanders Belgium
Posts: 88
point 1 is interesting because its better under than on the same plane, i thought around the traces was better :p but everybody makes mistakes :p so i will adjust that.
2: I know the clearances and they have been respected, but on this printscreen its very badly visible and its in 3D view mode. xS
And its already built around a heatsink that i have laying around :p I have spacers that will keep the heatsink isolated from the board. The drill holes for the mounting of the heatsink on the board haven't been drawn yet ;)
The newly posted images were only to give an idea of the design :p So i can adapt things like drill holes, copper planes en placement of the GDT and the CT's according to what tips and comments i receive. To avoid having to do it al over XD
I have built my DRSSTC bridge on a double sided pcb, with the same copper patterns on both sides connected in parallel to reduce losses. Apparently I am not suffering any problems with parasitic inductances, but honestly I have not scoped bridge waveforms yet.
IGBTs are mounted on the bottom side near the edge of the pcb with their body parallel to the pcb and sticking out of it to allow for easy mounting on to the heat sink. See drawing and photo attached below.
Tested up to about 400A, 230V rectified, 1.2m spark length.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
700nH ESL seems awfully high even for a big electrolytic. To put it in perspective, my OLTC2 primary (1 turn 10" diameter) was something like 600 or 800nH. I think the true ESL of that cap will be something like 25nH.
Tomorrow I'll post a PCB layout of a bridge that worked well for me.
Registered Member #1854
Joined: Wed Dec 10 2008, 06:09PM
Location: West-Flanders Belgium
Posts: 88
Well thanks for the replies,
Ive bought another 2 BHC busscaps 2200µF 400V So now i have 3.
I will use 2 of them.
I've made the first posted PCB layout and im going to test it, technically it was made before the post was made, because i was quite excited. But i have another eurocard to make a second and that will be the improved version.
I will test this first design, then later the improved version. And then compare the results :)
I will also split the 10µF MKT cap in to two 5µF MKP caps on each side on the bus. It will help in decoupling.
@ maurizzio
The first design on the page is also with the IGBT's sticking out sideways and then mounted on a large heatsink. Also on the bottom on the PCB, but its drawn at the top (it stays the same as long as you don't rotate the IGBT). I will see how much result i will get with that.
@ Steve
Well if the ESL is much lower, then the voltage of the spike wil be lesser. So thats positive.
And to receive a low inductance H-bridge design from one of the pionneers in tesla coiling is an honor :p
I also saw a technique, i think it was on your site. It places the MMC caps in such a way that the magnetic fields cancel each other out. Thus reducing the leakage inductance. I also tried to apply that in my resonant cap design. I hope it has some positive effect on the behavior of the primary circuit.
But thanks for the comments, I've done some power electronics at school but never completed a DRSSTC so the experiences of other coilers are helping me bigtime :p
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Voila This design uses two miniblock IGBTs and has clocked up many hours of runtime at 220kHz and a 300A current limit.
The positive and negative DC bus conductors are stacked for minimum inductance, but near the IGBTs they break apart to satisfy the high voltage clearance requirement.
Registered Member #1854
Joined: Wed Dec 10 2008, 06:09PM
Location: West-Flanders Belgium
Posts: 88
Thats a nice and neat set up.
And using normal lytics with solder connections. Mostly you see coils with a beefed up coke can sized bus capacitor with bolt connections.
But its really a nice setup, and the H-bridge board uses every possible way to lower the inductance. Nice touch with the centrifugal fan :p
i'd really wish i had mini brick IGBT's. Those things are much more robust. But i'm in belgium and those bricks cost a whole lot on farnell. Around 40 euro's a piece. I don't know the current exchange rate from euro's to dollars but its probably more in US dollars.
And if i'd go with digikey i need to pay alot of toll to ship the minibricks from America to Europe.
But i am gonna take a closer look to your bridge design, to see if i can pickup a few pointers. Like what priors over what ... (this is bad english XP its litterally translated from dutch to english )
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