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Electronic variac for (DR)SSTCs

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Maurizio Valvo

Fri Jan 13 2012, 11:26PM

Registered Member #3219 Joined: Mon Sept 20 2010, 09:06PM
Location: LeinÃ¬ (Turin), Italy
Posts: 23

I have designed an electronic variac based on the reverse phase (or trailing edge) dimmer principle to replace a bulky traditional variac in (DR)SSTC operation. I have tried to keep this design as simple as possible, even if it implements an average current limitation (to avoid blowing fuses) and expecially also a peak current limitation and short circuit protection (to save silicon).

The variac operates on the rectified mains supply with no galvanic isolation and is based on a common NE555 IC which drives directly an IGBT. In the schematic at the bottom R3 represents the load (1.9kW in this example) and C4 the Tesla coil bus capacitor. Potentiometer R7 regulates the bus voltage from around 30V to full rectified 230VAC mains voltage. The circuit can be easily adapted for different mains voltages.

I would appreciate any feedback or suggestion about this design. Has anyone tried anything similar?

Thanks,
Maurizio

Cicruit explanation
The trigger signal provided to the NE555 through R2 makes it drive the IGBT to the on state at the time when the rectified mains voltage approaches zero. The NE555 drives the IGBT off after a delay set by the potentiometer R7 which is used to control the amount of the mains half wave used to charge the bus capacitor C4, thus controlling the bus voltage.

Resistor R9 is used to sense the current through the IGBT and:
- U3 is used for the average current limitation (high time constant of R10/c5) by controlling the reference voltage of the NE555; the current limit is set by modifying R12
- U4 is used for peak current limitation and short circuit protection by resetting the NE555 (which causes the IGBT to turn off) when the instantaneus current reaches a predefined threshold, set by R19

The circuit is fed in a simple way by the rectified mains voltage through R8, C6 and a 18V zener (D7+D8).

The high value of C1 prevents the circuit to start when the supply voltage is not yet sufficient to drive the IGBT safely into saturation; it realizes also a soft start functionality because C4 voltage increases slowly with increasing reference voltage on the CV input of U1.

Circuit simulation results
The first set of graphs below shows a start up followed by a short circuit condition at time 2s, lasting for 500ms. You can easily see the soft start behaviour and the intervention of the peak current limitation (to about 145A) during the short circuit condition.

The second set of graphs below shows the behaviour of the average current limitation (R12 set to 99k): after the start up phase lasting around 1.5s current is limited to around 3,2A and voltage is decreased accordingly.

Power dissipation of the IGBT is always less than 10W, except during the short start up phases when it reaches almost 12W. Even with a higher load (R3=30ohm, corresponding to 3kW) power dissipation of the IGBT is normally limited to less than 17W.

Schematic

Soft start, short circuit, normal operation

Average current limitation

Steve Conner

Sat Jan 14 2012, 12:23PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

Yes, I've built two based on SCRs with ordinary phase angle firing, and they work great. I chose SCRs because they're cheaper and easier to protect than IGBTs. So I used generously sized SCRs and didn't bother with current limiting, and so far any time something has gone wrong, a fuse or breaker blew before any SCRs did. My biggest setup had a 92A semikron SCR brick and a 20A breaker.

I must steal your current limiting circuit :)

See scopeboy.com/tesla/drsstc for the Mk2 one.

Maurizio Valvo

Sat Jan 14 2012, 11:29PM

Registered Member #3219 Joined: Mon Sept 20 2010, 09:06PM
Location: LeinÃ¬ (Turin), Italy
Posts: 23

Thank you, Steve. I know your circuit (your site is in my TC favorites list

) and was really considering to build it. However I am a bit worried about the high peak currents through the bus capacitor due to the leading edge regulation. Even with my the trailing edge design, I am struggling not to exceed the rms current limits of my bus capacitor.

Steve Conner

Sun Jan 15 2012, 10:20AM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

Well, the power frequency ripple current from the rectifier should be pretty insignificant compared to the HF ripple current coming from the inverter part of the Tesla coil.

I used a big inductor to spread out the current pulses and improve the power factor. Also I avoid running the inverter section at full power with the DC bus voltage set low. When set to 100% both our circuits should behave the same as a plain uncontrolled diode rectifier.

Maurizio Valvo

Mon Jan 16 2012, 07:25PM

Registered Member #3219 Joined: Mon Sept 20 2010, 09:06PM
Location: LeinÃ¬ (Turin), Italy
Posts: 23

Oh yes, you are right: I didn't take into account the rms current generated by TC operation. I hope my bus capacitor will tolerate it: according to my rough simulations it is more than twice the rated one!

Thanks a lot for your feedback. If I decide to go forward and implement my circuit I will post results (it will take weeks ...).

Steve Conner

Mon Jan 16 2012, 08:00PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

Don't worry, the RMS ripple current rating is for continuous operation. When running a DRSSTC, your neighbours would call the police before the capacitor reached its steady state temperature.

I'm interested to see how your circuit turns out

Tartan5

Thu Jan 24 2013, 07:29PM

Registered Member #7963 Joined: Thu Nov 08 2012, 09:06PM
Location: Maine
Posts: 4

How well would this circuit perform for light loads, say 100W and under? Would you be willing to post the ASC file?

Thanks!

Maurizio Valvo

Sat Jan 26 2013, 09:17AM

Registered Member #3219 Joined: Mon Sept 20 2010, 09:06PM
Location: LeinÃ¬ (Turin), Italy
Posts: 23

Hi, thanks for your interest in this project!

I have further developed this circuit after testing, mainly because the 50Hz trigger didn't work reliably and (if I remember well ... I am no longer working on it since long time) to cope with the startup behaviour of the NE555 which I didn't take into account before. I have fully tested the circuit with a load composed by a much smaller bus capacitor (< 1000uF) and various resistive loads (even with no load, to answer your question), but I have not tested it yet with my TC (I have stopped for some time now, but plan to do it in the near future).

In summary, these are the changes I have done: trigger pulses are now generated by Q1 and Q2 and the circuitry around them; the J1 fet and its gate circuitry keep the NE555 in the reset status at power on to block undesired output pulses during this phase; C18 and R4 block the trigger input during power on; R26, C14 and R29 block the trigger input for some time after an ouptut pulse has been generated to avoid retriggering (which happened probably because of noise generated on the line by the IGBT switch-on with high loads).

C19 represents the TC bus capacitor; R15, S1 and B2 simulate the bursty TC load. D15 with V2 simulate the TVS that protects the IGBT from overvoltages. The rest of the circuit should be clear enough.

Note that component values indicated with blue text are the values to be used if you build the circuit; if you see a different value assigned to the component (black text) this is just to speed up simulation. I need to set the solver to "alternate" in order to run the simulation without errors (simulate -> control panel -> spice -> engine .. solver -> alternate).

You should easily find the additional component and model libraries that I used, if not just PM me (I am not sure I can post them here).

Regards,
Maurizio

]tesla_dimmer_10.2.asc.zip[/file]

Maurizio Valvo

Thu Aug 14 2014, 05:02PM

Registered Member #3219 Joined: Mon Sept 20 2010, 09:06PM
Location: LeinÃ¬ (Turin), Italy
Posts: 23

Hi all,

after long time of inactivity, I have recently tested the electronic variac with my DRSSTC: unfortunately I have to report a bad success

.

It did work apparently well, but after a few tests I had a failure: the TVS protecting the IGBT got shorted. After lots of thinking, investigation and further simulations, I have understood the cause of the failure: the peak current limiter was set to more than 200A and it intervened regularly at start up due to the high current necessary to load the bus capacitor. Unfortunately interruption of this high current combined with mains inductance produces huge voltage peaks across the IGBT which the TVS cannot withstand. I have read that mains inductance can reach hundreds of uHs and with such values I did not find any way to absorb the voltage spikes: I thought about slowing down IGBT switch off or adding a snubber network, but both solutions would imply a lot of power dissipation. If the peak current limiter is set too low, the bus cap would not charge sufficiently during TC operation.

So, unless anyone has a good idea how to solve this problem, I would say that trailing edge regulation is not usable for DRSSTCs and will stop this development.

Steve, I think I will seriously reconsider your solution!

Steve Conner

Thu Aug 14 2014, 09:09PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

Sorry to hear this didn't work out.

One advantage of SCRs is that they can't fry themselves with inductive kickback because they can't turn off while current is flowing. If you are going to use IGBTs, I think you should just go all the way and make a buck converter with PWM.

I've now built 3 copies of the Mk2 circuit. One of them went to the USA and ran off 60Hz.

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