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Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
You seemed to have just pasted sections of my designs into one, and it backfired. I am not surprised. Anyway, the gate driver section you made is messed up, it doesnt keep the output mosfet gate drive at the proper levels when the circuit is at rest and this messes it up when it tries to start up. I suggest you work at understanding this gate driver in more detail.
Why wont it start up? Lets assume the CLK signal is 0 at rest. Interrupter comes in and enables Q\ to HI. U4 gate driver does nothing at its output as its non-inverting. U3 gate driver goes HI output as its inverting, but, this only serves to turn ON Q1. Now, we have Q2 and Q4 both in OFF state, and Q1 turns on, this accomplishes practically nothing since there is no voltage across the GDT output... huh... If instead we feed in a signal generator into the feedback input, we will now end up clocking U3 gate driver input high (sending U3 output low), this will then turn on Q3 (and off Q1), which will now put 24V across GDT output and start things going. This is why i had to implement different control logic on the newer "UD" designs, using the UCC3732X enable function does not work with the P/N driver bridges, period. The reason is that you'd need both a state transition in the feedback input after the drivers are enabled, to 1) set up the P-ch drive capacitor bias, and then 2, turn on the Pfet. My driver maintains proper P-ch drive capacitor bias (caps C9 and C10) by keeping the gate drivers ON between interrupter pulses, so that only one gate driver has to drive its output LOW to start the whole thing off.
I guess its easy to overlook these problems untill you actually design a gate driver yourself.
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Brick DRSSTC final check
