My first DRSSTC
Marko, Mon Apr 03 2006, 07:27PMFinally a continuation of my DRSSTC project. (some changes here on 24. 6.)
Primary was far harder job than I tought, I couldnt get copper pipe right, it just get worse after each attempt of bending.
I ended using thinner (2,7mm) wire finally to end that agony.
For the beggining, some pics,, topic is (of course) going to be updated with progress.
New secondary: Fres with toroid ~120kHz (toroid is still too small)
Primary cap: 125nF
Primary inductance: about 15 uH
Halfbridge of 30N60's.
320VDC full supply voltage.
A mock-up of ATX box to shield electronics (proved to be pain to work with, and completly unnecessary).
pics of primary former construction:
I measured the resonant frequency, and it seems to be about 400kHz.
Calculated frequency was a bit more than 300, so that worries me.
I picked up almost exact 2,5us period on the scope, despite a bit blurry waveform on 1us divide:
update: april 15., 2006.
finished interrupter, ON time potentiometer is that small hole (as I need it to be somewhat public-proof). I dont want someone (or me) to flip the pot accidentaly and blow the coil up because of too high on-time.
Update, may 16.
Finished and tested control board.
I got quite good waveform at output, nonpolar elecrolytic cap seems to quiet up ringing a bit but transistents aren't any faster than with normal caps.
Gate resistors of 3,9ohms slow the thing down a bit, I guess diodes will help there a bit (faster fall time) so let's say it's OK too.
Adding a 3,9 ohm resistor in paralell with cap (any) helps too, but I don't know how safe it is.
Last cycle seems to periodically dissapear, I can tune interrupter and RC timing circuit not to do it but it usually returns after a while.
I also saw this in other's waveforms so I think (i hope) it's normal.
Cycle is always full so there will be no hard-switching.
One thing I added is interrupter failsafe circuit.
Firstly it is a resistive divider at interruptr input pin (to HC14) that divides the input voltage by about 3 (1K and 2,2K resistors)
If nothing is connectedit pulls the input of HC14 down so coil doesn't go on and explodes. Divider also saves HC14 from getting overvoltage on input (interrupter works at 15V so I get about 5V at input when high). It takes about 8-9 volts to actually pull it high, so there is no chance for accidental turnon.
Another thing is the pNP transistor that pulls interrupter output strongly down if enable signal goes eakly low. I use spare wire in the cable to carry back +15V to the base of transistor so it's off when interrupter is connected.
Actually resistor divider worked that good that there was no need of that, so it seems that it's only use will be just to turn on red led if interrupter is disconnected
Update may 17:
MMC, 125nF, 3.2kV (8x1uF 400V in series)
Caps are MKT, not the best but I hope they'l work for beggining.
Resistors are behind, 6,8 megaohm on each cap.
Update 24.6.
Coil recently saw first light.
It's a bit mocked around the table but it's in running state.
I had problems with primary feedback, as it would oscillate only cycle or two and break down(??) causng poor output, no matter what on time I used.
I checked everything on board again and it was fine.
Rewound transformers are also fine.This left me no choice but to use antenna. (
)I plugged the coil into mains, and got a 3cm streamer.
I saw something was wrong, and soon figured out that part of wire from top of the secondary fell deeply into it and arced over. It burned a hole in secondary, but it's just barely aestethic.
I repaired this and coil responded with nice 35cm streamer, on the pic down there.
I got carried away and operated at sick ON-times,v probably I got over half amicrosecond (altough I promised myself to keep under 200us).
Sparks looked pretty nice, CW, and hot.
Then I turned the coil off, tried to tune the primary, and instantly - IGBT died
I guess I made it too much away from ZCS, and it was already on the edge of dying..
Interestingly murphy law thing didn't work this time - another IGBT was alright, but ofcourse I replaced both.
On 100V coil barely gave 8cm spark, not quite good.
Now I got a clue how to make primary feedback working - I seriesed a resistor directly with transformer output (I had to do this, no matter tha all conponents on that part probed fine).
Firstly it was 1k. It made the thing work during full ON period (
) but current was leaping a bit. It increased almost by 50% of current before.Now I increased he resistor to 10k and finally got a fine primary oscillation.
The big question remains, how do other coils do that without my stupid resistor?
It seems like diodes are overloading CT or something, but everything is completely fine.
In-built 1k resistor (after zeners) doesn't help here.
Now with primary feedback going I did low power tests again, at 100V I get 20cm sparks
But that again requires high ON-time and high bang rate, probably about a kilohertz.
I'm scared to give it full power yet. ZCS looks good to me, here are some pics and closeups.
20, 10 and 5 us div. Curent is just 20A because I was overloading power supply, it can give just a single shot at 100V so now i'm at some 20-30V.
Rectangular thing is gate signal of one IGBT. I had to slope it and trigger misses a bit at beggining. It's probably a trait of running both probes simultaneously.
...
Re: My first DRSSTC
Marko, Sat Apr 08 2006, 02:21PM
Edit: I finished my interrupter, and beginning work on main control electronics.
Also I un-messed up the thread a bit, so all the information goes into the first post.
Marko, Sat Apr 08 2006, 02:21PM
Edit: I finished my interrupter, and beginning work on main control electronics.
Also I un-messed up the thread a bit, so all the information goes into the first post.
Re: My first DRSSTC
Desmogod, Tue May 16 2006, 07:27AM
Surely the interrupter would be better off in a shielded box?
Desmogod, Tue May 16 2006, 07:27AM
Surely the interrupter would be better off in a shielded box?
Re: My first DRSSTC
HV Enthusiast, Tue May 16 2006, 11:44AM
Not necessarily. I never run my interruptors in shielded boxes, and considering most people run all their electronics underneath their DRSSTCs with no shielding and then go through the trouble with shielding the interruptor box is a bit silly. Or better yet, i've seen people run shielded interruptors and run non-shielded cables from the interruptor to the control electronics.
HV Enthusiast, Tue May 16 2006, 11:44AM
Desmogod wrote ...
Surely the interrupter would be better off in a shielded box?
Surely the interrupter would be better off in a shielded box?
Not necessarily. I never run my interruptors in shielded boxes, and considering most people run all their electronics underneath their DRSSTCs with no shielding and then go through the trouble with shielding the interruptor box is a bit silly. Or better yet, i've seen people run shielded interruptors and run non-shielded cables from the interruptor to the control electronics.
Re: My first DRSSTC
Steve Ward, Tue May 16 2006, 06:33PM
My original interrupter was not shielded. It was fine *most* of the time, but if you brought it too close to the coil the frequency would increase a bit. The layout could affect this alot, and my layout was nothing to be desired
.
The only suggestion i have is to put a bigger toroid on the coil. I usually make the toroid diameter equal to the secondary length. It just looks right in my opinion, and bigger toroids give better performance usually.
Steve Ward, Tue May 16 2006, 06:33PM
My original interrupter was not shielded. It was fine *most* of the time, but if you brought it too close to the coil the frequency would increase a bit. The layout could affect this alot, and my layout was nothing to be desired
.The only suggestion i have is to put a bigger toroid on the coil. I usually make the toroid diameter equal to the secondary length. It just looks right in my opinion, and bigger toroids give better performance usually.
Re: My first DRSSTC
Marko, Tue May 16 2006, 08:49PM
OK, board is done too.
Can I ask one small question: should I ground the GND of low voltage circuit, or i should just leave it and just put interrupter cable shield to the ground and leave everything else hang?
Marko, Tue May 16 2006, 08:49PM
OK, board is done too.
Can I ask one small question: should I ground the GND of low voltage circuit, or i should just leave it and just put interrupter cable shield to the ground and leave everything else hang?
Re: My first DRSSTC
Steve Conner, Tue May 16 2006, 10:20PM
All of my drivers have the "Odd jumping of last cycle" effect. It's a side effect of the sync circuit that only allows you to end the burst at zero crossings. I don't know if Steve Ward's design does it.
Steve Conner, Tue May 16 2006, 10:20PM
All of my drivers have the "Odd jumping of last cycle" effect. It's a side effect of the sync circuit that only allows you to end the burst at zero crossings. I don't know if Steve Ward's design does it.
Re: My first DRSSTC
Marko, Tue May 16 2006, 10:24PM
This is steve ward's, it's obivously caused by RC and bistable (sync circuit) reacting on irregularities on interrupter signal. I guess it's irrelevant then.
Marko, Tue May 16 2006, 10:24PM
This is steve ward's, it's obivously caused by RC and bistable (sync circuit) reacting on irregularities on interrupter signal. I guess it's irrelevant then.
Re: My first DRSSTC
HV Enthusiast, Wed May 17 2006, 12:34AM
In regards to Steve Ward's sync circuit, it (the circuit) does exhibit metastability problems or in otherwords, it can produce illegal states at the output of the flip-flop if you go through it and look at the waveforms. Not sure if this is a real issue in operation, but if you go through the calculations and simulations in PSPICE you can definitely see the illegal states.
Perhaps, this is what you could be seeing.
I have caught on a number of times the flip-flop latching up in this type of circuit (my synch circuit is very similar but has an extra flip-flop) during operation and staying high from time to time during the intrapulse period of operation.
HV Enthusiast, Wed May 17 2006, 12:34AM
In regards to Steve Ward's sync circuit, it (the circuit) does exhibit metastability problems or in otherwords, it can produce illegal states at the output of the flip-flop if you go through it and look at the waveforms. Not sure if this is a real issue in operation, but if you go through the calculations and simulations in PSPICE you can definitely see the illegal states.
Perhaps, this is what you could be seeing.
I have caught on a number of times the flip-flop latching up in this type of circuit (my synch circuit is very similar but has an extra flip-flop) during operation and staying high from time to time during the intrapulse period of operation.
Re: My first DRSSTC
Marko, Wed May 17 2006, 01:09PM
Upated again.
I've done the most of work now, I am only awaiting 30N60's from group buy yet. They are sent in april and still no signs.
Coil may see first light (or explosion) soon depending on that.
And maybe I could add a bigger toroid atop of this later.
Marko, Wed May 17 2006, 01:09PM
Upated again.
I've done the most of work now, I am only awaiting 30N60's from group buy yet. They are sent in april and still no signs.
Coil may see first light (or explosion) soon depending on that.
And maybe I could add a bigger toroid atop of this later.
Re: My first DRSSTC
Steve Ward, Wed May 17 2006, 06:10PM
The extra cycle thing at the end only occurs if you are using a VCO, because the *first* cycle is not synced with the interrupter (like it would be in real operation). The only condition that can cause that in real operation is by setting the interrupter timing *just* on the edge, but it doesnt matter really, its a perfectly safe condition.
Dan, i cannot find these illegal states. Ive gone through every possible sequence of events with the flip flop, and all conditions are predictable. The only possible problem is if S! and R! (Clr! and Pre!) go high simultaneously, which is pretty much impossible with my circuit. The circuit works perfectly for me, ive never had a problem with it. If you can point out the illegal state, id appreciate it. This is the schematic im using:
Steve Ward, Wed May 17 2006, 06:10PM
The extra cycle thing at the end only occurs if you are using a VCO, because the *first* cycle is not synced with the interrupter (like it would be in real operation). The only condition that can cause that in real operation is by setting the interrupter timing *just* on the edge, but it doesnt matter really, its a perfectly safe condition.
Dan, i cannot find these illegal states. Ive gone through every possible sequence of events with the flip flop, and all conditions are predictable. The only possible problem is if S! and R! (Clr! and Pre!) go high simultaneously, which is pretty much impossible with my circuit. The circuit works perfectly for me, ive never had a problem with it. If you can point out the illegal state, id appreciate it. This is the schematic im using:
Re: My first DRSSTC
Steve Conner, Wed May 17 2006, 06:48PM
Shh Dan! Don't use the "M" word.
Metastability is what you get when the data input to the flip-flop changes exactly as the clock is changing state. The flip-flop can't decide whether to accept the new data or reject it and hold the old stuff. What happens is undefined. The probability of hitting it at exactly the "wrong" time is very small, but if you do hit the sore point, the output can stick for a relatively long time before it makes its mind up. I think Dan was saying that some flip-flops can lose the plot completely and put their Q and Q' outputs in the same state.
All SSTC drivers that use flip-flops will suffer from this problem, including my PLL design. I knew about metastability and the possibility of illegal states when I designed it, and put two flip-flops in a row to make the odds of it happening a good deal steeper.
One electronics text I know of uses Jean Buridan's paradox to illustrate this effect. A dog is placed midway between two identical bowls of dog food and it's supposed to starve to death because it can't decide which to eat first. My driver circuit eats both and takes a whiz on your trouser leg.
Steve Conner, Wed May 17 2006, 06:48PM
Shh Dan! Don't use the "M" word.
Metastability is what you get when the data input to the flip-flop changes exactly as the clock is changing state. The flip-flop can't decide whether to accept the new data or reject it and hold the old stuff. What happens is undefined. The probability of hitting it at exactly the "wrong" time is very small, but if you do hit the sore point, the output can stick for a relatively long time before it makes its mind up. I think Dan was saying that some flip-flops can lose the plot completely and put their Q and Q' outputs in the same state.
All SSTC drivers that use flip-flops will suffer from this problem, including my PLL design. I knew about metastability and the possibility of illegal states when I designed it, and put two flip-flops in a row to make the odds of it happening a good deal steeper.
One electronics text I know of uses Jean Buridan's paradox to illustrate this effect. A dog is placed midway between two identical bowls of dog food and it's supposed to starve to death because it can't decide which to eat first. My driver circuit eats both and takes a whiz on your trouser leg.
Re: My first DRSSTC
HV Enthusiast, Wed May 17 2006, 06:59PM
One of the problem conditions is when the PRE and CLR are simultaneously LOW. This produces a state where both Q and Q' are HIGH.
This occurs on each rising edge of your interruptor pulse. When the interruptor goes HIGH, the CLR input on the JK goes LOW at this same time, because of the RC delay, the PRE input on the JK remains low for about 15us putting the flip-flop into a metastable state during this time. When the flip-flop is in a metastable condition, the outputs are undetermined and will tend to oscillate between logic 0 and 1.
Of course, the condition usually removes itself when either PRE or CLR goes HIGH again, but for 15us you have a condition where both Q and Q' are undetermined and maybe oscillating between 0 and 1.
Of course, as you said, it may not be an issue with the application you are using. Typically, you can generally tolerate metastable states so long as the clock period is greater than the time it takes for a metastable state to resolve itself to a stable condition.
As you said, your circuit may work perfectly okay, but as i pointed out, the metastable condition does exist on every interruptor pulse.
HV Enthusiast, Wed May 17 2006, 06:59PM
One of the problem conditions is when the PRE and CLR are simultaneously LOW. This produces a state where both Q and Q' are HIGH.
This occurs on each rising edge of your interruptor pulse. When the interruptor goes HIGH, the CLR input on the JK goes LOW at this same time, because of the RC delay, the PRE input on the JK remains low for about 15us putting the flip-flop into a metastable state during this time. When the flip-flop is in a metastable condition, the outputs are undetermined and will tend to oscillate between logic 0 and 1.
Of course, the condition usually removes itself when either PRE or CLR goes HIGH again, but for 15us you have a condition where both Q and Q' are undetermined and maybe oscillating between 0 and 1.
Of course, as you said, it may not be an issue with the application you are using. Typically, you can generally tolerate metastable states so long as the clock period is greater than the time it takes for a metastable state to resolve itself to a stable condition.
As you said, your circuit may work perfectly okay, but as i pointed out, the metastable condition does exist on every interruptor pulse.
Re: My first DRSSTC
Marko, Sat Jun 24 2006, 06:37PM
A new update, 'real' first light finally. And also new interesting problems with primary feedback..
Marko, Sat Jun 24 2006, 06:37PM
A new update, 'real' first light finally. And also new interesting problems with primary feedback..
Re: My first DRSSTC
Reaching, Sat Jun 24 2006, 07:02PM
mhh, maybe you can describe the new interesting problems a bit?
Reaching, Sat Jun 24 2006, 07:02PM
mhh, maybe you can describe the new interesting problems a bit?
Re: My first DRSSTC
Marko, Sat Jun 24 2006, 07:41PM
It's all in the first post. With primary feedback oscillation collapsed after few cycles, but later I found it working good with 10K resistor in series with CT output.
I found no bugs multimetering the input stage (diodes, cap, resistor..), problem seems to be a bit deeper that that.
Marko, Sat Jun 24 2006, 07:41PM
It's all in the first post. With primary feedback oscillation collapsed after few cycles, but later I found it working good with 10K resistor in series with CT output.
I found no bugs multimetering the input stage (diodes, cap, resistor..), problem seems to be a bit deeper that that.
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