A 16 bit CPU implemented in 7400 series logic

Bjørn, Sun Feb 12 2006, 09:50AM

A high performance 16 bit RISC CPU
Harvard style architecture that executes all instructions in a single clock cycle.
8 registers, the program counter is mapped to register number 8.
Conditional execution of all instructions.
Condition flags are set on demand.
All instructions execute in a single clock cycle.
Branch-link instruction where the program counter is copied to R6.
Register bank with two read ports and one write port, all accessed during the same cycle.

Huge schematics
Emulator and assembler
Instruction Set

It is not optimized for size or speed. I have tried to route a dual layer PCB for it without any luck. There are about 130 chips in the schematics.
Re: A 16 bit CPU implemented in 7400 series logic
Tim Koene, Tue Feb 14 2006, 08:24AM

Wow Bjoern,

Amazing work! I might soon have a way to make huge circuit boards. Perhaps you could split it into 4 smaller boards which *can* be routed? Just a suggestion.

Re: A 16 bit CPU implemented in 7400 series logic
Bjørn, Tue Feb 14 2006, 09:45AM

Splitting it up might be a usable solution, maybe some sort of backplane where each functional unit is a card. That way instructions can be added or improved by just swapping cards.
Re: A 16 bit CPU implemented in 7400 series logic
..., Tue Feb 14 2006, 03:00PM

wow, this reminds me of the magic-1 computer; I find it really amazing how a bunch of simple logic gates can be used to make an intelligent being... Heck, I can telnet into magic over the internet and play games on it!

Keep up the good work!
Re: A 16 bit CPU implemented in 7400 series logic
Hazmatt_(The Underdog), Tue Feb 14 2006, 10:29PM

looks cool!

also looks like another 8051, *waits for verbal abuse*
Re: A 16 bit CPU implemented in 7400 series logic
JimG, Wed Feb 15 2006, 08:07PM

After designing a number of ALUs by hand in college I have become fascinated with implementations that others have done.

Have you simulated your CPU yet?

I was really impressed by the magic-1 computer when I first heard about it. I was a little let down to see that it used 74f381s to do its math operations, but it's understandable considering that the machine was already fairly complex for a wire wrapped computer.
Re: A 16 bit CPU implemented in 7400 series logic
Bjørn, Wed Feb 15 2006, 10:47PM

Yes, it runs fine in a digital simulator. It has not ben run in a full simulation and I don't know of any programs that are capable of doing it in a simple way. It would not be very interesting since the design of the PCB would be the most important variable anyway.


When it comes to 8051 I have taken great care to avoid most Intel ideas.
Re: A 16 bit CPU implemented in 7400 series logic
Carbon_Rod, Thu Feb 16 2006, 03:03AM

Most people use VHDL and build fpga based systems etc.. for fun...
(small units with a loader can be well under $75.-)

I have some 8" Si wafer if you want to make your own chips :D

Protel says it can do this sort of thing, but I have never tried it with the proto-shops system. Also, multisim (now part of NI) can do VHDL (extra plugin) so it should be pretty easy to import or build a sim Block.

Synopsys can build/sim ASICs just fine, but it is hard to get terminal time with and is an insane price.

UMPS (Universal Microprocessor Simulator) was an old block design tool that could build and test core designs. It had a Academic trial too if you can find this old program. (a few meg)

I was going to have a look at this GPL VHDL project to see how well it would import into the other systems (let me know what you think if you get time to try it out):
Link2

The 8051 & 8052 VHDL free model is around too if you need an example.
check here: Link2
Re: A 16 bit CPU implemented in 7400 series logic
Bjørn, Thu Feb 16 2006, 03:41AM

The intended target actually is a FPGA, it is 16 bit so it will fit well with the RAM in a Spartan II. I found that VHDL takes away much of the fun so I tested it in a way that was painless and interesting.

The register bank will be mapped to a RAM block so it will have 32 sets of register for fast context switching. Since the RAM has two read/write ports the Harvard architecture will disappear.
Re: A 16 bit CPU implemented in 7400 series logic
Carbon_Rod, Thu Feb 16 2006, 06:39AM

Very cool, B)
This book are OK if you need some low-level VHDL intro tips:
Vhdl Programming By Example
Douglas Perry

Also, we both know that often what works on one small chip will not scale-up to 74HCxxx series DIPs on a PCB. The old systems use to have almost a one-to-one ratio of filter caps to chip. What Clock speed did you want?

Note the French air-force did build a fully gate based U.A.V. a few years back.

Yep... Protel (now altium) used to sell a $2300.00 devel kit for in system fpga simulation on a real proto board. Now they say you do not even need to know VHDL to build a system (fpga Demo cost only a few hundred $ now):
Link2
Re: A 16 bit CPU implemented in 7400 series logic
Hazmatt_(The Underdog), Thu Feb 16 2006, 07:22AM

For simulations Multisim I agree would be comparativily easy

Or if you have access at College to Cadence, there's that option, however...Specter sucks and causes a lot of delays! its really touchy..really touchy!
Re: A 16 bit CPU implemented in 7400 series logic
Bjørn, Thu Feb 16 2006, 09:54AM

This book are OK if you need some low-level VHDL intro tips:
I will look into it, I have had a look in quite a few books without finding anything remotely what I am looking for. I don't want simulation and I don't want workflow. I just need the tricks I need to make a CPU in one page of code in one afternoon.


What Clock speed did you want?
1 MHz would be plenty, it is much more efficient than most classic microprocessors so it does not need a high frequency to be useful. On the FPGA I am hoping for 10 MHz without messing around with pipelining or 20 MHz if it has to use two clock cycles for each instruction. I am not sure how it will work out with reading and writing to the register bank on the same cycle on a FPGA.


I have used Proteus VSM to check that it runs programs correctly.
Re: A 16 bit CPU implemented in 7400 series logic
Carbon_Rod, Thu Feb 16 2006, 11:54PM

At 20 MHz your limit should be around 10 to 15 metres absolute trace length maximum minus (n * gate settling times + m*clock settling time + p*latch settling time etc.) may limit this further.

Circuit and bus cross-talk was a far more serious problem then systems of today. But I have seen systems running at only a few MHz run into noise related problems.

The nice thing with total clock control is you can ramp up the clock once it is working to find out exactly where the board turns chaotic and know your max clock speed.

I like Harvard architecture in many ways. But finding a decent compiler skeleton for it is practically impossible (Unless the intended audience is all Forth programmers.)

It is true though, finding books and material about core designs is not everyday reading. One of the old systems I reverse engineered had a bunch of ISA style plugs on a bus board with power etc. and all parts (CPU had several boards) would plug into it. I thought it was funny because it seemed rather familiar to the relatively more recent industrial units, and the removable Mac motherboard designs.

Technology seems to travels in cycles, I hear even magnetic RAM may make a comeback. (Not a joke... Shiver...)
Re: A 16 bit CPU implemented in 7400 series logic
Hazmatt_(The Underdog), Fri Feb 17 2006, 12:32AM

MIT is working on mag ram right now actually!

but once we have quantum transistors, they'll probably beat out mag ram 100 fold.