Half Bridge Layout

gentoo_daemon, Sun Apr 01 2007, 05:50AM

Hey guys/gals,
This is what I'm planning for the half bridge. Go ahead and give it a sanity check. Link2

The snubbers total to about 14 uF.

Re: Half Bridge Layout
Steve Ward, Sun Apr 01 2007, 07:42AM

Looks fine, just make the physical layout very low inductance (mount the DC electrolytic caps as close to the IGBTs as possible, and make all connections short and wide). Depending on what IGBTs you use, you might find that a laminate bus structure would suit your needs (see my DRSSTC 2 page for an example).
Re: Half Bridge Layout
gentoo_daemon, Sun Apr 01 2007, 02:56PM

I'll make a note of that Steve.
I've been reading the DRSSTC-2 page very closely. I really can't afford to blow any IGBTs. One thing I must ask you. After experiencing IGBT failure, you tried a 20 ohm resistor at the gate. did it really help with those transients?
Re: Half Bridge Layout
Steve Ward, Sun Apr 01 2007, 10:56PM

Its hard to say if the higher resistance helped or not. The problem is that while it slows the switching speed (lessening di/dt), it increases the current being switched because of the time delay. I think i ended up with 5 or 10 ohms ultimately. The 5.1 ohms you show is probably a good start for the gate resistance particularly because you are trying to use a GDT for the IGBTs (which will be a little slower on the transition times than my direct drive).