DRSSTC 2 SIMULATION PROBLEMS
gentoo_daemon, Sat Feb 10 2007, 06:39PMHello.
My name is Rick. I'm a brand new member, and a beginner solid state coiler. I'm trying to reproduce Steve Ward's DRSSTC 2. Before I start building, I wanted to understand/simulate his interrupt and driver circuitry. I am using workbench multisim 9.0 to simulate his basic interrupter found on his design guide. I'm inputting a 42 kHz sine wave to simulate the feedback from the coil, and observing the output of the JK flip flop with the multisim O-scope.
The problem is that the output ~Q goes high for a few periods, and then stays low (much like a 1-shot). Initially I believed the problem maybe the astable 555 (the one with 2 POTS) since it wasn't changing states, I replaced with a different configurations, but then ~Q stays on the high state.
From my understanding Steve's design is supposed to clip the feedback sine wave, add some hysteresis, and pass it through the JKFF, which is configured to be a T FF since both the inputs are tied high. With the input at the clk, wouldn't this just cut the feedback frequency in half? The astable 555 sets the duty cycle while the comparator and 1-shot make sure it is in sync with the feedback. Feel free to correct my understanding.
I've attached the multisim circuit as well as a JPEG screen shot.
Here are links just in case
Any ideas?
-Rick.
Re: DRSSTC 2 SIMULATION PROBLEMS
Steve Ward, Sat Feb 10 2007, 08:18PM
Its not a T FF, its acting as a SET. When the 555 astable is high, the ~Q output is forced high by the /clear input. When the 555 astable falls low, this then allows the FF to act as a FF, with J and K tied high (Note that K input is INVERTED!) the next clock input should force ~Q low. The only function of this flip flop is to stop gate drive at a current zero crossing (synchronizing, if you will). Your simulation has K tied low (meaning it will be a toggle FF, you DONT want this).
There are of course other ways of wiring the FF to do the same thing.
You may want to have your simulation toggle the SET once at the start of your simulation, i know this is required in pspice before you try doing anything with the flip flops (supposing you want them to work properly).
Let me know if the purpose of the flip flop is still unclear to you. Also note that the clock signal (derived from the feedback) is also fed into the gate drivers. The FF only controls the ENABLE of the drivers. The result should be a train of clock pulses that is then shut down at a rising clock edge after the 555 timer falls low.
Steve Ward, Sat Feb 10 2007, 08:18PM
Its not a T FF, its acting as a SET. When the 555 astable is high, the ~Q output is forced high by the /clear input. When the 555 astable falls low, this then allows the FF to act as a FF, with J and K tied high (Note that K input is INVERTED!) the next clock input should force ~Q low. The only function of this flip flop is to stop gate drive at a current zero crossing (synchronizing, if you will). Your simulation has K tied low (meaning it will be a toggle FF, you DONT want this).
There are of course other ways of wiring the FF to do the same thing.
You may want to have your simulation toggle the SET once at the start of your simulation, i know this is required in pspice before you try doing anything with the flip flops (supposing you want them to work properly).
Let me know if the purpose of the flip flop is still unclear to you. Also note that the clock signal (derived from the feedback) is also fed into the gate drivers. The FF only controls the ENABLE of the drivers. The result should be a train of clock pulses that is then shut down at a rising clock edge after the 555 timer falls low.
Re: DRSSTC 2 SIMULATION PROBLEMS
gentoo_daemon, Sun Feb 11 2007, 07:45PM
thanks steve.
I'll change the pins on the JKFF.
There are 3 pots on the circuit . Around what values did you set those to?
Also I wanted to use just your basic interrupter found in your design guide with the bigger EUPEC IGBTs. In other words, I don't plan on using the boost converter found under the DRRSTC2 section. The mosfet drivers will be connected to the 1:2:2 GDT and then to the half bridge. Do you think this will work okay?
gentoo_daemon, Sun Feb 11 2007, 07:45PM
thanks steve.
I'll change the pins on the JKFF.
There are 3 pots on the circuit
. Around what values did you set those to? Also I wanted to use just your basic interrupter found in your design guide with the bigger EUPEC IGBTs. In other words, I don't plan on using the boost converter found under the DRRSTC2 section. The mosfet drivers will be connected to the 1:2:2 GDT and then to the half bridge. Do you think this will work okay?
Re: DRSSTC 2 SIMULATION PROBLEMS
Steve Ward, Wed Feb 14 2007, 05:56AM
Your setup sounds OK. Really, though, its hard to drive big IGBTs with a GDT. You will probably want to parallel more gate drivers on the output.
As to the pot settings, they are supposed to work at very wide ranges. The only one that should be "set" is the pot that sets the Vref on the LM311 comparator (this sets the current limit level). If you know the ratio of your CT, the burden resistance, and the current you want to limit too, you can figure out roughly where this pot should be set. Say you have 1000A primary current max, and a 1000:1 CT ratio, that means 1A at the CT output. Say its got 10 ohms loading it, that gives 10V across the resistor. Thus, you would want to set Vref to 10V. This doesnt account for the diode drop of the full wave rectifier on the CT, so you would end up limiting too high. Its best to use trial and error.
Steve Ward, Wed Feb 14 2007, 05:56AM
Your setup sounds OK. Really, though, its hard to drive big IGBTs with a GDT. You will probably want to parallel more gate drivers on the output.
As to the pot settings, they are supposed to work at very wide ranges. The only one that should be "set" is the pot that sets the Vref on the LM311 comparator (this sets the current limit level). If you know the ratio of your CT, the burden resistance, and the current you want to limit too, you can figure out roughly where this pot should be set. Say you have 1000A primary current max, and a 1000:1 CT ratio, that means 1A at the CT output. Say its got 10 ohms loading it, that gives 10V across the resistor. Thus, you would want to set Vref to 10V. This doesnt account for the diode drop of the full wave rectifier on the CT, so you would end up limiting too high. Its best to use trial and error.
Re: DRSSTC 2 SIMULATION PROBLEMS
gentoo_daemon, Thu Feb 22 2007, 05:58AM
Steve
When you say place the drivers in parallel, you mean place two GDTs in parallel to drive one IGBT, and not two ti ucc37322/1 mosfet drivers in parallel to drive one GDT correct?
So I would end up having to use two 37322s, each with their own GDTs, and then those GDT would be in parallel?
Same for the 37321s?
What do you think is more likely to destroy the IGBTs, over current from a badly built OCD circuit, or having too high of a duty cycle from the 555? the 4hv wiki mentions that igbt failure usually occurs instantaneously, so I want to do much as possible to avoid it.
Thanks again.
gentoo_daemon, Thu Feb 22 2007, 05:58AM
Steve
When you say place the drivers in parallel, you mean place two GDTs in parallel to drive one IGBT, and not two ti ucc37322/1 mosfet drivers in parallel to drive one GDT correct?
So I would end up having to use two 37322s, each with their own GDTs, and then those GDT would be in parallel?
Same for the 37321s?
What do you think is more likely to destroy the IGBTs, over current from a badly built OCD circuit, or having too high of a duty cycle from the 555? the 4hv wiki mentions that igbt failure usually occurs instantaneously, so I want to do much as possible to avoid it.
Thanks again.
Re: DRSSTC 2 SIMULATION PROBLEMS
Steve Ward, Thu Feb 22 2007, 09:27PM
No, the exact opposite. You only need 1 GDT winding per IGBT gate, but you will want higher current drive on the primary of the GDT. Paralleling windings doesnt help unless your primary has a lower impedance source. But in general, R(gdt) << R(driver) so you dont need to parallel windings or anything but you do want to parallel the gate driver chips for lower resistance on their output.
Steve Ward, Thu Feb 22 2007, 09:27PM
When you say place the drivers in parallel, you mean place two GDTs in parallel to drive one IGBT, and not two ti ucc37322/1 mosfet drivers in parallel to drive one GDT correct?
No, the exact opposite. You only need 1 GDT winding per IGBT gate, but you will want higher current drive on the primary of the GDT. Paralleling windings doesnt help unless your primary has a lower impedance source. But in general, R(gdt) << R(driver) so you dont need to parallel windings or anything but you do want to parallel the gate driver chips for lower resistance on their output.
Re: DRSSTC 2 SIMULATION PROBLEMS
Steve Ward, Thu Feb 22 2007, 09:29PM
No, the exact opposite. You only need 1 GDT winding per IGBT gate, but you will want higher current drive on the primary of the GDT. Paralleling windings doesnt help unless your primary has a lower impedance source. But in general, R(gdt) << R(driver) so you dont need to parallel windings or anything but you do want to parallel the gate driver chips for lower resistance on their output.
Well... both aspects are highly controllable. You are more likely to lose an IGBT from poor bridge design, which can promote voltage spikes across the IGBTs. And of course the failure is instantaneous, its either working fine or its blown, so im not sure what the HV wiki meant by that.
Steve Ward, Thu Feb 22 2007, 09:29PM
When you say place the drivers in parallel, you mean place two GDTs in parallel to drive one IGBT, and not two ti ucc37322/1 mosfet drivers in parallel to drive one GDT correct?
No, the exact opposite. You only need 1 GDT winding per IGBT gate, but you will want higher current drive on the primary of the GDT. Paralleling windings doesnt help unless your primary has a lower impedance source. But in general, R(gdt) << R(driver) so you dont need to parallel windings or anything but you do want to parallel the gate driver chips for lower resistance on their output.
What do you think is more likely to destroy the IGBTs, over current from a badly built OCD circuit, or having too high of a duty cycle from the 555? the 4hv wiki mentions that igbt failure usually occurs instantaneously, so I want to do much as possible to avoid it.
Well... both aspects are highly controllable. You are more likely to lose an IGBT from poor bridge design, which can promote voltage spikes across the IGBTs. And of course the failure is instantaneous, its either working fine or its blown, so im not sure what the HV wiki meant by that.
Re: DRSSTC 2 SIMULATION PROBLEMS
Steve Conner, Thu Feb 22 2007, 11:10PM
Well, if there's stuff in the HV Wiki that you disagree with, please edit it!
And don't believe anything you see in a simulation 
Steve Conner, Thu Feb 22 2007, 11:10PM
Well, if there's stuff in the HV Wiki that you disagree with, please edit it!
And don't believe anything you see in a simulation Re: DRSSTC 2 SIMULATION PROBLEMS
gentoo_daemon, Wed Feb 28 2007, 05:03PM
thanks for your patience Steve.
I'm having trouble picturing the feedback ferrite core transformers (1:33).
http://stevehv.4hv.org/DRSSTC1/controller1.JPG
In this case, you are using primary feedback (?). is it okay to use such a small gauge of wire to wrap that 1 turn considering that 2 of these transformer will go in series with the primary LC? Does this not raise the impedance?
gentoo_daemon, Wed Feb 28 2007, 05:03PM
thanks for your patience Steve.
I'm having trouble picturing the feedback ferrite core transformers (1:33).
http://stevehv.4hv.org/DRSSTC1/controller1.JPG
In this case, you are using primary feedback (?). is it okay to use such a small gauge of wire to wrap that 1 turn considering that 2 of these transformer will go in series with the primary LC? Does this not raise the impedance?
Re: DRSSTC 2 SIMULATION PROBLEMS
Bennem, Wed Feb 28 2007, 06:36PM
Hi Gentoo,
I beleive that picture of Steves is when he used secondary feedback,
so that picture is of his secondary cable going through the ferrite core.
hence the lower gauge of wire.
Bennem, Wed Feb 28 2007, 06:36PM
Hi Gentoo,
I beleive that picture of Steves is when he used secondary feedback,
so that picture is of his secondary cable going through the ferrite core.
hence the lower gauge of wire.
Re: DRSSTC 2 SIMULATION PROBLEMS
gentoo_daemon, Thu Mar 01 2007, 01:44AM
thanks Bennem
What would be the advantages of using feedback from the primary? Secondary feedback can be substituted for this.
And for over current detection in the primary, I'm thinking about using these high current shunts
It's basically a real rugged, linear resistor so the current can be measured as a proportion of the voltage across it. Let me know what you guys think.
gentoo_daemon, Thu Mar 01 2007, 01:44AM
thanks Bennem
What would be the advantages of using feedback from the primary? Secondary feedback can be substituted for this.
And for over current detection in the primary, I'm thinking about using these high current shunts
It's basically a real rugged, linear resistor so the current can be measured as a proportion of the voltage across it. Let me know what you guys think.
Re: DRSSTC 2 SIMULATION PROBLEMS
Bennem, Thu Mar 01 2007, 06:31AM
Hi Gentoo,
Allthough secondary feedback works, the current in the
secondary coil is not completely represenative of the
current in the primary coil.
To acheive zero current switching, which is what we want,
the best method feedback for a DRSSTC presently
is primary feedback. IMO.
Bennem, Thu Mar 01 2007, 06:31AM
Hi Gentoo,
Allthough secondary feedback works, the current in the
secondary coil is not completely represenative of the
current in the primary coil.
To acheive zero current switching, which is what we want,
the best method feedback for a DRSSTC presently
is primary feedback. IMO.
Re: DRSSTC 2 SIMULATION PROBLEMS
Steve Ward, Thu Mar 01 2007, 08:00PM
Firstly, let me say that my design is particularly that way for a reason (ive blown up enough silicon figuring it out, so everyone else shouldnt have to).
The picture you linked was of the secondary feedback, and is thusly out of date. Do not use secondary feedback! As Ben said, primary feedback ensures zero current switching (aside from switching delays) and is much more robust.
On the first 1:33 turn CT, you dont need to "wind" a primary, just slip the ferrite toroid with 33 turns on it, around the primary conductor, from the output of the bridge. Do not put the CT on the node connecting the L and the C as the voltage rings up to many kV at this node!
Current shunts: why would you want to use a shunt??? This would require your controller/driver board be connected to the H-bridge directly. This is why CTs exist!!! Not to mention that a CT will *undoubtedly* give a cleaner signal of the current through the primary.
Steve Ward, Thu Mar 01 2007, 08:00PM
Firstly, let me say that my design is particularly that way for a reason (ive blown up enough silicon figuring it out, so everyone else shouldnt have to).
The picture you linked was of the secondary feedback, and is thusly out of date. Do not use secondary feedback! As Ben said, primary feedback ensures zero current switching (aside from switching delays) and is much more robust.
On the first 1:33 turn CT, you dont need to "wind" a primary, just slip the ferrite toroid with 33 turns on it, around the primary conductor, from the output of the bridge. Do not put the CT on the node connecting the L and the C as the voltage rings up to many kV at this node!
Current shunts: why would you want to use a shunt??? This would require your controller/driver board be connected to the H-bridge directly. This is why CTs exist!!! Not to mention that a CT will *undoubtedly* give a cleaner signal of the current through the primary.
Re: DRSSTC 2 SIMULATION PROBLEMS
Dr. Drone, Thu Mar 01 2007, 10:38PM
Dr. Drone, Thu Mar 01 2007, 10:38PM
Re: DRSSTC 2 SIMULATION PROBLEMS
ragnar, Fri Mar 02 2007, 12:51AM
Chris, those epoxy-dipped CTs are really sexy! I remember when you posted the pics of them earlier. Tell me, is the field well constrained to within the ferrite core? If you put them side by side, do the cascaded CTs get confused?
Matt
ragnar, Fri Mar 02 2007, 12:51AM
Chris, those epoxy-dipped CTs are really sexy! I remember when you posted the pics of them earlier. Tell me, is the field well constrained to within the ferrite core? If you put them side by side, do the cascaded CTs get confused?
Matt
Re: DRSSTC 2 SIMULATION PROBLEMS
Steve Ward, Fri Mar 02 2007, 06:42AM
BP, given that the permeability of the core is 1000-10,000 times that of air, what would you conclude ?
(hint: yes, you can bunch up CTs very close to eachother with no problems).
Steve Ward, Fri Mar 02 2007, 06:42AM
BP, given that the permeability of the core is 1000-10,000 times that of air, what would you conclude ?
(hint: yes, you can bunch up CTs very close to eachother with no problems).
Re: DRSSTC 2 SIMULATION PROBLEMS
gentoo_daemon, Fri Mar 02 2007, 02:35PM
Christopher_R,
Those pictures really hammered the idea in. Thank you
gentoo_daemon, Fri Mar 02 2007, 02:35PM
Christopher_R,
Those pictures really hammered the idea in. Thank you
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