What is a "low impedance" DRSSTC? More theory
Steve Conner, Sat May 24 2014, 04:28PMMy recent Odin disaster got me thinking about this subject.
From looking at the test results, it seemed obvious that the coil wanted more current than the inverter could safely deliver, but how could this be quantified?It struck me that it is possible to write the following equations:
1: Inverter output impedance = (4/pi)*(1/sqrt(2))*(Vbus/Iocd) where Vbus is the DC bus voltage and Iocd is the current limit setting.
Note that if the coil is running in the steady state with primary current just below the current limit (the condition we want to design for) then the inverter output impedance must be equal to the resistive part of the streamer load impedance, as reflected into the primary.
2: Primary surge impedance = sqrt(Lp/Cp) = 1/(2*pi*fres*Cp) = 2*pi*fres*Lp
Finally 3: Primary loaded Q = Primary surge impedance/Inverter output impedance
I calculated the primary loaded Q for my old DRSSTC (Mjollnir) according to this formula. It worked out as 12.5 with the old 50nF tank capacitor, and 6.25 with the 100nF replacement. In both cases the coil performed well and was easy to drive with a PLL driver.
For Odin in its current state (80kHz fres, 0.75uF tank cap, 1000A current limit) I got only 2.3. Experimentally I found the primary ringup was violently quick and the PLL driver didn't seem to like it much at all.
Also, Uspring recently posted that maximum power transfer is achieved when Qsec = 1/k. My old "hungry streamer" theory suggests that Qsec will indeed tend to 1/k under heavy streamer loading and this will set an ultimate limit to streamer growth.
So I would argue from this that the primary should be designed for a loaded Q of at least 1/k too. If Qpri=Qsec=1/k then we have a critical coupled bandpass filter. My Odin design also fails this rule of thumb as it has k=0.225 which implies Qpri should be greater than 4.4.
Qpri is also roughly equal to the number of cycles the unloaded primary would take to ring up to the current limit. Again this more or less agrees with the test results from Odin and Mjollnir. Hitting the current limit in 2 cycles means there is no time to transfer much energy to the secondary or resolve the two resonant modes. But in 6 cycles it all seems to work much more smoothly.
I welcome any comments from Uspring, Antonio etc. I would also be interested to see values of loaded Q according to this formula from other DRSSTC builders. In the meantime I will go ahead and change the Odin primary circuit to have a loaded Q of between 4.4 and 6.5, and see what happens.
Re: What is a "low impedance" DRSSTC? More theory
Mads Barnkob, Sat May 24 2014, 08:01PM
You also have your relatively high primary current to frequency ratio to thank for the low Q, you are already running with a rather small topload, add some more!
So far I have only tested my large DRSSTC (
) with a static load, plotting its numbers (38kHz, 0,8uF, 1500A, 564VDC, gives me a Primary loaded Q of 10,9 with the corrected equation from Uspring
Mads Barnkob, Sat May 24 2014, 08:01PM
You also have your relatively high primary current to frequency ratio to thank for the low Q, you are already running with a rather small topload, add some more!
So far I have only tested my large DRSSTC (
) with a static load, plotting its numbers (38kHz, 0,8uF, 1500A, 564VDC, gives me a Primary loaded Q of 10,9 with the corrected equation from UspringRe: What is a "low impedance" DRSSTC? More theory
Uspring, Sat May 24 2014, 08:03PM
You wrote:
Qpri = (Qsec/k^2) * (1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec)
The "PLL upper pole - primary tuned low" operation can make the (1 - f^2/fsec^2) term very low, so that the first term becomes negligible.
Qpri is different from loaded Q. Qpri determines how far primary current ramps up, loaded Q how fast. It is a good idea to make loaded Q similar to Qpri, since then arc loading will limit primary current to a value near Iocd. Although the above equation is exact, changes of Qsec, fsec and f due to arc loading make estimates fragile.
The only part I understand about the hungry streamer model is its prediction of the phase between arc voltage and arc current being 45 degrees. That's close zo my measurements but that part doesn't make any prediction about Qsec.
Uspring, Sat May 24 2014, 08:03PM
You wrote:
1: Inverter output impedance =(4/pi)*(1/sqrt(2))*(Vbus/Iocd) where Vbus is the DC bus voltage and Iocd is the current limit setting.It looks like you have a different definition of Vbus than I. For a half bridge switching between +Vbus and -Vbus I get an impedance of (4/pi)*(Vbus/Iocd).
Finally 3: Primary loaded Q = Primary surge impedance/Inverter output impedanceThis then is a measure of how many cycles it takes until the OCD is hit if there is no secondary (and arcs).
Also, Uspring recently posted that maximum power transfer is achieved when Qsec = 1/k. My old "hungry streamer" theory suggests that Qsec will indeed tend to 1/k under heavy streamer loading and this will set an ultimate limit to streamer growth.That really depends on the way you tune. For the "PLL upper pole - primary tuned low" operation, the optimal Qsec might be higher. This is based on the equation below:
Qpri = (Qsec/k^2) * (1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec)
The "PLL upper pole - primary tuned low" operation can make the (1 - f^2/fsec^2) term very low, so that the first term becomes negligible.
Qpri is different from loaded Q. Qpri determines how far primary current ramps up, loaded Q how fast. It is a good idea to make loaded Q similar to Qpri, since then arc loading will limit primary current to a value near Iocd. Although the above equation is exact, changes of Qsec, fsec and f due to arc loading make estimates fragile.
The only part I understand about the hungry streamer model is its prediction of the phase between arc voltage and arc current being 45 degrees. That's close zo my measurements but that part doesn't make any prediction about Qsec.
Re: What is a "low impedance" DRSSTC? More theory
Steve Conner, Sat May 24 2014, 08:37PM
You could well be right, if 4/pi is the ratio between the peak of the fundamental, and the amplitude of the square wave. I thought it was the RMS.
All I am basically proposing for a hypothesis is that no matter how hard you drive the primary of a DRSSTC, you will never be able to grow a streamer big enough to get the secondary loaded Q below 1/k, because if it ever did drop below 1/k, the power transfer would start to decrease and the streamer would therefore get smaller. If this is true, we could possibly work it backwards to calculate the impedance of streamers from observations of spark length and primary current.
Steve Conner, Sat May 24 2014, 08:37PM
Uspring wrote ...
It looks like you have a different definition of Vbus than I. For a half bridge switching between +Vbus and -Vbus I get an impedance of (4/pi)*(Vbus/Iocd).
It looks like you have a different definition of Vbus than I. For a half bridge switching between +Vbus and -Vbus I get an impedance of (4/pi)*(Vbus/Iocd).
You could well be right, if 4/pi is the ratio between the peak of the fundamental, and the amplitude of the square wave. I thought it was the RMS.
wrote ...
It is a good idea to make loaded Q similar to Qpri, since then arc loading will limit primary current to a value near Iocd.
This is exactly what I just realised. So I just assumed loaded Q equal to Qpri and worked the math backwards. Interestingly, if the first term in your equation is very small, we get Qpri*Qsec = (1/k^2), and Qpri=Qsec=1/k is a solution of that.It is a good idea to make loaded Q similar to Qpri, since then arc loading will limit primary current to a value near Iocd.
wrote ...
The only part I understand about the hungry streamer model is its prediction of the phase between arc voltage and arc current being 45 degrees. That's close zo my measurements but that part doesn't make any prediction about Qsec.
The hungry streamer model says that any sort of discharge will develop until it is drawing all the power that the source can supply. It's probably not a very good model for Tesla coil streamers because a discharge to air is "ballasted" by its own capacitance. But I think that as the streamers become large compared to the size of the coil, it might become more accurate, because the equivalent series capacitance will become small compared to the output impedance of the coil.The only part I understand about the hungry streamer model is its prediction of the phase between arc voltage and arc current being 45 degrees. That's close zo my measurements but that part doesn't make any prediction about Qsec.
All I am basically proposing for a hypothesis is that no matter how hard you drive the primary of a DRSSTC, you will never be able to grow a streamer big enough to get the secondary loaded Q below 1/k, because if it ever did drop below 1/k, the power transfer would start to decrease and the streamer would therefore get smaller. If this is true, we could possibly work it backwards to calculate the impedance of streamers from observations of spark length and primary current.
Re: What is a "low impedance" DRSSTC? More theory
Antonio, Sun May 25 2014, 12:53AM
I would avoid considerations of Q, since the system is not a second-order circuit, and consider the impedance that the inverter wants to see, considering the maximum input current and the maximum voltage applied to the primary:
R=(4/pi)*Vmax/Imax
And then design the system as an impedance matching network to match this impedance to the impedance at the secondary. The required calculations are in my site:
The formulas for the doubly terminated case can be worked to produce the following:
Given the secondary inductance and capacitance, Lb and Cb, and the primary capacitance Ca:
Required primary inductance La=Lb*Cb/Ca+Ca*R^2 (note the last term. This is not a SG Tesla coil where La*Ca=Lb*Cb, although the difference is small).
Driving frequency F=1/(2*Pi*sqrt(Lb*Cb)). The secondary resonance.
Voltage gain: n=sqrt(Lb/Ca)/R. The assumed load is then R*n^2.
Bandwidth, if the primary side had R in series:
B=Ca*R*sqrt(2)/(2*Pi*Lb*Cb)
Coupling coefficient: k=sqrt(B^2/(2F^2+B^2))
The number of cycles for stabilization of the output is approximately F/B.
Note that this design is the same obtained for the lossless case for a certain R and a certain mode, since the tuning relations are identical.
These designs are idealized. Apply the usual discount of secondary capacitance considering capacitive streamer loading.
About the formula:
Qpri = (Qsec/k^2) * (1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec)
I don't understand how Qpri can depend on f (driving frequency?)
My formulas above give k aproximately equal to 1/Qsec if k is low, and Qpri almost equal to Qsec if the primary is alone and loaded with R.
Antonio, Sun May 25 2014, 12:53AM
I would avoid considerations of Q, since the system is not a second-order circuit, and consider the impedance that the inverter wants to see, considering the maximum input current and the maximum voltage applied to the primary:
R=(4/pi)*Vmax/Imax
And then design the system as an impedance matching network to match this impedance to the impedance at the secondary. The required calculations are in my site:
The formulas for the doubly terminated case can be worked to produce the following:
Given the secondary inductance and capacitance, Lb and Cb, and the primary capacitance Ca:
Required primary inductance La=Lb*Cb/Ca+Ca*R^2 (note the last term. This is not a SG Tesla coil where La*Ca=Lb*Cb, although the difference is small).
Driving frequency F=1/(2*Pi*sqrt(Lb*Cb)). The secondary resonance.
Voltage gain: n=sqrt(Lb/Ca)/R. The assumed load is then R*n^2.
Bandwidth, if the primary side had R in series:
B=Ca*R*sqrt(2)/(2*Pi*Lb*Cb)
Coupling coefficient: k=sqrt(B^2/(2F^2+B^2))
The number of cycles for stabilization of the output is approximately F/B.
Note that this design is the same obtained for the lossless case for a certain R and a certain mode, since the tuning relations are identical.
These designs are idealized. Apply the usual discount of secondary capacitance considering capacitive streamer loading.
About the formula:
Qpri = (Qsec/k^2) * (1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec)
I don't understand how Qpri can depend on f (driving frequency?)
My formulas above give k aproximately equal to 1/Qsec if k is low, and Qpri almost equal to Qsec if the primary is alone and loaded with R.
Re: What is a "low impedance" DRSSTC? More theory
Steve Conner, Sun May 25 2014, 07:41AM
Interesting. I saw your doubly terminated Butterworth method before, but didn't really understand it at the time. I think I understand a little more now.
The one problem I still have with it is this: it allows you to design a coil to drive a given streamer load, but it doesn't say anything about whether the coil design will be suitable for following the trajectory that develops that value of streamer load, or whether it would just trigger the current limit before the streamer has a chance to develop. In your article you said:
Do you have a formula that relates the change in input resistance to the change in load resistance? This would help to visualise the trajectory that the system would follow as the streamer load developed. My mental picture is of some sort of parabolic curve, the input resistance is maximal for a load that gives roughly Q=1/k and decreases in both directions from there. It must decrease in both directions because the input resistance is zero for load resistances of both zero and infinity.
Also, does it follow that the only thing that can change the voltage gain of the system is reactive loading by the streamer capacitance? I think for stable operation we want the voltage gain to decrease somewhat with streamer loading. There are some tunings (mistunings?) that cause it to increase.
Steve Conner, Sun May 25 2014, 07:41AM
Interesting. I saw your doubly terminated Butterworth method before, but didn't really understand it at the time. I think I understand a little more now.
The one problem I still have with it is this: it allows you to design a coil to drive a given streamer load, but it doesn't say anything about whether the coil design will be suitable for following the trajectory that develops that value of streamer load, or whether it would just trigger the current limit before the streamer has a chance to develop. In your article you said:
wrote ...
If the actual resistive load is different, the input impedance remains resistive, and the voltage gain doesn't change, because with both LC tanks tuned the system reduces to an ideal transformer with voltage gain n.
If the actual resistive load is different, the input impedance remains resistive, and the voltage gain doesn't change, because with both LC tanks tuned the system reduces to an ideal transformer with voltage gain n.
Do you have a formula that relates the change in input resistance to the change in load resistance? This would help to visualise the trajectory that the system would follow as the streamer load developed. My mental picture is of some sort of parabolic curve, the input resistance is maximal for a load that gives roughly Q=1/k and decreases in both directions from there. It must decrease in both directions because the input resistance is zero for load resistances of both zero and infinity.
Also, does it follow that the only thing that can change the voltage gain of the system is reactive loading by the streamer capacitance? I think for stable operation we want the voltage gain to decrease somewhat with streamer loading. There are some tunings (mistunings?) that cause it to increase.
Re: What is a "low impedance" DRSSTC? More theory
Avalanche, Sun May 25 2014, 01:11PM
I'm probably going to make myself look stupid, but I can't understand why 'Iocd' enters into an equation calculating inverter output impedence of a voltage-source inverter if it is running in steady-state below it's current limit. As I understand it, 'Iocd' is a 'trip' level and the inverter doesn't become a current source at 'Iocd' (or does it, in a bang-bang fashion?)
Avalanche, Sun May 25 2014, 01:11PM
I'm probably going to make myself look stupid, but I can't understand why 'Iocd' enters into an equation calculating inverter output impedence of a voltage-source inverter if it is running in steady-state below it's current limit. As I understand it, 'Iocd' is a 'trip' level and the inverter doesn't become a current source at 'Iocd' (or does it, in a bang-bang fashion?)
Re: What is a "low impedance" DRSSTC? More theory
Steve Conner, Sun May 25 2014, 01:19PM
It does become a current source, at least with the cycle skipping method of current limiting I use (and a primary Q high enough that controlling the current in units of 1 cycle makes sense)
However, it is really more of a design thing. You decide how much current your bridge can safely put out, and then my formula helps you design a resonator to match it. The details of how the current limit works don't really matter. The formula only needs to know the current limit so it can avoid triggering it, if you like.
Steve Conner, Sun May 25 2014, 01:19PM
It does become a current source, at least with the cycle skipping method of current limiting I use (and a primary Q high enough that controlling the current in units of 1 cycle makes sense)
However, it is really more of a design thing. You decide how much current your bridge can safely put out, and then my formula helps you design a resonator to match it. The details of how the current limit works don't really matter. The formula only needs to know the current limit so it can avoid triggering it, if you like.
Re: What is a "low impedance" DRSSTC? More theory
Antonio, Sun May 25 2014, 10:51PM
Due to the design the input impedance is "maximally resistive" around the driving frequency, meaning that even with quite large changes in the driving frequency it remains resistive.
The phase of the input impedance crosses zero with zero inclination at the driving frequency. This may cause a problem with a PLL controller using the primary current for feedback. If it is designed to keep the designed driving frequency with no load, when the phase goes from +90 to -90 degrees at the central frequency, exactly at the point where the load resistance drops to the designed value the PLL will move the driving frequency away, because the phase inclination changes sign. A controller that just follows the sign of the input current apparently would work correctly.
With no load the input current shows beats that rise to approximately the same level of the designed maximum input current, if the driving frequency is kept at the designed place. With losses the beats decay soon.
A PLL controller may be set to operate at one of the resonances with no load, where the phase rises. It would then move to the central frequency correctly as the load decreases, but I don't know to what level the input current will rise in the way. It depends on how the streamers develop and can't be predicted with a linear model.
I created this design based on a Butterworth filter years ago, but didn't pay much attention to it, concentrating on the lossless design, that seems to work in the same way. I see now that the equivalence is not exact. Verifying why.
Greater load capacitance reflects to the input as more capacitance too. If the driver can accept it, the voltage gain doesn't drop. If the driver tries to keep the zvs condition the system gets detuned, but as disproportionally great current is drained from the driver the voltage gain actually increases.
I have implemented the calculations from specified elements in my drsstcd program, and made some improvements in the plots too:
Antonio, Sun May 25 2014, 10:51PM
Steve Conner wrote ...
Do you have a formula that relates the change in input resistance to the change in load resistance? This would help to visualise the trajectory that the system would follow as the streamer load developed. My mental picture is of some sort of parabolic curve, the input resistance is maximal for a load that gives roughly Q=1/k and decreases in both directions from there. It must decrease in both directions because the input resistance is zero for load resistances of both zero and infinity.
Also, does it follow that the only thing that can change the voltage gain of the system is reactive loading by the streamer capacitance? I think for stable operation we want the voltage gain to decrease somewhat with streamer loading. There are some tunings (mistunings?) that cause it to increase.
If just the resistive load RL changes the input impedance is just RL/n^2, as if an ideal transformer were used.Do you have a formula that relates the change in input resistance to the change in load resistance? This would help to visualise the trajectory that the system would follow as the streamer load developed. My mental picture is of some sort of parabolic curve, the input resistance is maximal for a load that gives roughly Q=1/k and decreases in both directions from there. It must decrease in both directions because the input resistance is zero for load resistances of both zero and infinity.
Also, does it follow that the only thing that can change the voltage gain of the system is reactive loading by the streamer capacitance? I think for stable operation we want the voltage gain to decrease somewhat with streamer loading. There are some tunings (mistunings?) that cause it to increase.
Due to the design the input impedance is "maximally resistive" around the driving frequency, meaning that even with quite large changes in the driving frequency it remains resistive.
The phase of the input impedance crosses zero with zero inclination at the driving frequency. This may cause a problem with a PLL controller using the primary current for feedback. If it is designed to keep the designed driving frequency with no load, when the phase goes from +90 to -90 degrees at the central frequency, exactly at the point where the load resistance drops to the designed value the PLL will move the driving frequency away, because the phase inclination changes sign. A controller that just follows the sign of the input current apparently would work correctly.
With no load the input current shows beats that rise to approximately the same level of the designed maximum input current, if the driving frequency is kept at the designed place. With losses the beats decay soon.
A PLL controller may be set to operate at one of the resonances with no load, where the phase rises. It would then move to the central frequency correctly as the load decreases, but I don't know to what level the input current will rise in the way. It depends on how the streamers develop and can't be predicted with a linear model.
I created this design based on a Butterworth filter years ago, but didn't pay much attention to it, concentrating on the lossless design, that seems to work in the same way. I see now that the equivalence is not exact. Verifying why.
Greater load capacitance reflects to the input as more capacitance too. If the driver can accept it, the voltage gain doesn't drop. If the driver tries to keep the zvs condition the system gets detuned, but as disproportionally great current is drained from the driver the voltage gain actually increases.
I have implemented the calculations from specified elements in my drsstcd program, and made some improvements in the plots too:
Re: What is a "low impedance" DRSSTC? More theory
Uspring, Mon May 26 2014, 03:40PM
Antonio wrote:
Consideration of Qpri is a means to match the inverter to the coil. It really makes sense only for a steady state situation, i.e. when currents and voltages in the coil have settled to constant values. The input resistance Rinp of the system should be equal to the output resistance of the inverter. From the definition of Qpri:
Qpri = Primary surge impedance / Rinp = sqrt(Lp/Cp) / Rinp
Rinp can be calculated once Qpri is known.
Rinp is a useful value. From it the max primary current can be calculated, the power transfer from primary to the secondary (i.e. Ipri^2 * Rinp). Also it can be determined if there is a good match between inverter and the coil, i.e. when Rinp = R.
Rinp is caused by secondary, i.e arc loading. Qpri is given by:
Qpri = (Qsec/k^2) * (1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec),
where f is the frequency the coil is driven at and fsec the secondary resonance frequency. As noted above, Rinp can be calculated from this. I like this form of Rinp derivation since the formula becomes relatively simple and does not contain any tank Ls and Cs explicitly.
For zero current switching, there is a choice of 3 different frequencies, the lower and upper pole and the center frequency. Maybe it is instructive to see, what this equation says for different tuning strategies. I've used Odin values as far as they are known to me. (80kHz fsec, 0.75uF tank cap, k=0.225
1. Center tuning, i.e. driving the coil at the center frequency fsec = 80kHz, primary tank tuned to the same f.
f is then equal to fsec and
Qpri = 1/(k^2 * Qsec) = 19.8 / Qsec
Since Qsec is proportional to the arc load resistance RL, Qpri is inversely proportional to it and Rinp then again proportional to RL as Antonio writes:
Qpri = 1.85 * Qsec + 19.8 / Qsec
2. Steves tuning, i.e. upper pole operation, primary tuned low, e.g. 70kHz.
The upper pole is then at f= 87kHz:
Qpri = 0.66 * Qsec + 19.8 / Qsec
Assuming again, that due to arc loading fsec drops to 70kHz and that the driving frequency f stays at the upper pole. The pole frequency is then f = 79.5kHz:
Qpri = 1.66 * Qsec + 19.8 / Qsec
3. Classical tuning, i.e. lower pole driving frequency, primary is tuned low to 70kHz. The driving frequency is then 67 kHz:
Qpri = 1.76 * Qsec + 19.8 / Qsec
With fsec = 70 KHz the lower pole is at 63.2 kHz:
Qpri = 0.66 * Qsec + 19.8 / Qsec
A large Qpri always means, that much current is needed for power transfer to the secondary. So a low Qpri is desirable. But possibly more important than this is, that Qpri shouldn't change too much during arc buildup, since that implies a mismatch between the inverter and the coil at one time or another. Qsec drops from maybe around a few hundred to about 3 to 10 at full arc length. In Steves tuning, the change in Qpri from light to heavy load is much smaller than in the classical tuning. The overshoot of primary current is thus avoided.
Center tuning is the best for light loads but gets worse for heavier. It is an interesting mode of operation if zero current switching can be accommodated.
Edit: Center tuning can be achieved under varying arc capacitances by adjusting inverter frequency in such a way, that the phase between primary and secondary current stays at 90 degrees. This will always give the lowest possible Qpri. This involves not switching at zero current at all times.
Steve wrote:
Uspring, Mon May 26 2014, 03:40PM
Antonio wrote:
I would avoid considerations of Q, since the system is not a second-order circuit, and consider the impedance that the inverter wants to see, considering the maximum input current and the maximum voltage applied to the primary:Edit: I agree, that formally Qpri is a doubtful concept, since it is not a property of the primary tank itself but depends on the whole system, which is not second order. See Qpri just as a way to express the real part of the input impedance Rinp. I liked this way of expressing Rinp, since it makes the equation indepent of explicit tank inductances and capacitances.
R=(4/pi)*Vmax/Imax
And then design the system as an impedance matching network to match this impedance to the impedance at the secondary.
Consideration of Qpri is a means to match the inverter to the coil. It really makes sense only for a steady state situation, i.e. when currents and voltages in the coil have settled to constant values. The input resistance Rinp of the system should be equal to the output resistance of the inverter. From the definition of Qpri:
Qpri = Primary surge impedance / Rinp = sqrt(Lp/Cp) / Rinp
Rinp can be calculated once Qpri is known.
Rinp is a useful value. From it the max primary current can be calculated, the power transfer from primary to the secondary (i.e. Ipri^2 * Rinp). Also it can be determined if there is a good match between inverter and the coil, i.e. when Rinp = R.
Rinp is caused by secondary, i.e arc loading. Qpri is given by:
Qpri = (Qsec/k^2) * (1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec),
where f is the frequency the coil is driven at and fsec the secondary resonance frequency. As noted above, Rinp can be calculated from this. I like this form of Rinp derivation since the formula becomes relatively simple and does not contain any tank Ls and Cs explicitly.
For zero current switching, there is a choice of 3 different frequencies, the lower and upper pole and the center frequency. Maybe it is instructive to see, what this equation says for different tuning strategies. I've used Odin values as far as they are known to me. (80kHz fsec, 0.75uF tank cap, k=0.225
1. Center tuning, i.e. driving the coil at the center frequency fsec = 80kHz, primary tank tuned to the same f.
f is then equal to fsec and
Qpri = 1/(k^2 * Qsec) = 19.8 / Qsec
Since Qsec is proportional to the arc load resistance RL, Qpri is inversely proportional to it and Rinp then again proportional to RL as Antonio writes:
If just the resistive load RL changes the input impedance is just RL/n^2, as if an ideal transformer were used.Assuming, that due to arc loading fsec drops to 70kHz and that the driving frequency f stays constant at 80 kHz:
Qpri = 1.85 * Qsec + 19.8 / Qsec
2. Steves tuning, i.e. upper pole operation, primary tuned low, e.g. 70kHz.
The upper pole is then at f= 87kHz:
Qpri = 0.66 * Qsec + 19.8 / Qsec
Assuming again, that due to arc loading fsec drops to 70kHz and that the driving frequency f stays at the upper pole. The pole frequency is then f = 79.5kHz:
Qpri = 1.66 * Qsec + 19.8 / Qsec
3. Classical tuning, i.e. lower pole driving frequency, primary is tuned low to 70kHz. The driving frequency is then 67 kHz:
Qpri = 1.76 * Qsec + 19.8 / Qsec
With fsec = 70 KHz the lower pole is at 63.2 kHz:
Qpri = 0.66 * Qsec + 19.8 / Qsec
A large Qpri always means, that much current is needed for power transfer to the secondary. So a low Qpri is desirable. But possibly more important than this is, that Qpri shouldn't change too much during arc buildup, since that implies a mismatch between the inverter and the coil at one time or another. Qsec drops from maybe around a few hundred to about 3 to 10 at full arc length. In Steves tuning, the change in Qpri from light to heavy load is much smaller than in the classical tuning. The overshoot of primary current is thus avoided.
Center tuning is the best for light loads but gets worse for heavier. It is an interesting mode of operation if zero current switching can be accommodated.
Edit: Center tuning can be achieved under varying arc capacitances by adjusting inverter frequency in such a way, that the phase between primary and secondary current stays at 90 degrees. This will always give the lowest possible Qpri. This involves not switching at zero current at all times.
About the formula:The secondary voltage depends on the driving frequency due to resonance effects. For a given arc load resistance the arc power consumption follows secondary voltage. Qpri or conversely, Rinp reflects that.
Qpri = (Qsec/k^2) * (1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec)
I don't understand how Qpri can depend on f (driving frequency?)
The phase of the input impedance crosses zero with zero inclination at the driving frequency.That depends on the secondary load. For a particular load this is true. For other loads the inclination is either positive or negative.
Steve wrote:
Do you have a formula that relates the change in input resistance to the change in load resistance? This would help to visualise the trajectory that the system would follow as the streamer load developed. My mental picture is of some sort of parabolic curve, the input resistance is maximal for a load that gives roughly Q=1/k and decreases in both directions from there. It must decrease in both directions because the input resistance is zero for load resistances of both zero and infinity.Maybe the above answers this question. In the ideal center tuning case Rinp is proportional to the arc load resistance. As soon as you get out of tune by arc detuning, Rinp has a max (or Qpri a min) between zero and infinite arc resistance, so your mental picture is correct.
Re: What is a "low impedance" DRSSTC? More theory
Antonio, Thu May 29 2014, 02:52AM
I now understand the meaning of Qpri depending on the frequency. It is just another form of expressing the real part of the input impedance of the system. Quite elegant. After some pages of algebra I managed to find the formula, but what I obtained was a bit different:
Qpri = (Qsec/k^2) * (fsec/f)^2*(1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec).
I assumed LpriCpri=LsecCsec for this.
As a numerical verification, Lpri=1, Cpri=1, Lsec=10, Csec=0.1, k=0.1, Rsec=10 results in Qsec=1, wsec=1 (rad/s), and Qpri=325 for w=2 rad/s. The other formula gives Qpri=1000.
A numerical simulation of the structure agrees with 325, with the real part of the input impedance being Rpri=sqrt(Lpri/Cpri)/Qpri=1/325 exactly at 2 rad/s.
For the tuning (1-k^2)LpriCpri=LsecCsec I get the same multiplied by (1-k^2)^0.5.
Please verify.
Antonio, Thu May 29 2014, 02:52AM
I now understand the meaning of Qpri depending on the frequency. It is just another form of expressing the real part of the input impedance of the system. Quite elegant. After some pages of algebra I managed to find the formula, but what I obtained was a bit different:
Qpri = (Qsec/k^2) * (fsec/f)^2*(1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec).
I assumed LpriCpri=LsecCsec for this.
As a numerical verification, Lpri=1, Cpri=1, Lsec=10, Csec=0.1, k=0.1, Rsec=10 results in Qsec=1, wsec=1 (rad/s), and Qpri=325 for w=2 rad/s. The other formula gives Qpri=1000.
A numerical simulation of the structure agrees with 325, with the real part of the input impedance being Rpri=sqrt(Lpri/Cpri)/Qpri=1/325 exactly at 2 rad/s.
For the tuning (1-k^2)LpriCpri=LsecCsec I get the same multiplied by (1-k^2)^0.5.
Please verify.
Re: What is a "low impedance" DRSSTC? More theory
Uspring, Thu May 29 2014, 12:56PM
You're right. Looking at my original equations I noticed, that I had used an incorrect "definition" for Qpri and Qsec, i.e.
Qpri = 2*pi*f*Lpri / Rinp and Qsec = RL / 2*pi*f*Lsec
instead of
Qpri = sqrt(Lpri/Cpri) / Rinp and Qsec = RL / sqrt(Lseci/Csec)
The values are similar but not the same. The correct equation is:
Qpri = (Qsec/k^2) * fpri*fsec/f^2*(1 - f^2/fsec^2)^2 + fpri/fsec*1/(k^2 * Qsec).
fpri is the primary resonance f. This holds also for Lpri*Cpri not equal to Lsec*Csec and coincides with your equation for Lpri*Cpri = Lsec*Csec.
Uspring, Thu May 29 2014, 12:56PM
You're right. Looking at my original equations I noticed, that I had used an incorrect "definition" for Qpri and Qsec, i.e.
Qpri = 2*pi*f*Lpri / Rinp and Qsec = RL / 2*pi*f*Lsec
instead of
Qpri = sqrt(Lpri/Cpri) / Rinp and Qsec = RL / sqrt(Lseci/Csec)
The values are similar but not the same. The correct equation is:
Qpri = (Qsec/k^2) * fpri*fsec/f^2*(1 - f^2/fsec^2)^2 + fpri/fsec*1/(k^2 * Qsec).
fpri is the primary resonance f. This holds also for Lpri*Cpri not equal to Lsec*Csec and coincides with your equation for Lpri*Cpri = Lsec*Csec.
Re: What is a "low impedance" DRSSTC? More theory
Antonio, Thu May 29 2014, 04:16PM
Ok. This formula covers all the tuning modes. Now the question is if just the real part of the input impedance is enough to predict the steady-state input current. The impedance seen by the driver is purely resistive at the central frequency and, if the load is light, at two other frequencies only. A driver trying to force zvs condition will track one of them. I imagine that a look at the expression for the imaginary part of the input impedance reveals what are these frequencies, that shall be put as f in the formula.
Antonio, Thu May 29 2014, 04:16PM
Ok. This formula covers all the tuning modes. Now the question is if just the real part of the input impedance is enough to predict the steady-state input current. The impedance seen by the driver is purely resistive at the central frequency and, if the load is light, at two other frequencies only. A driver trying to force zvs condition will track one of them. I imagine that a look at the expression for the imaginary part of the input impedance reveals what are these frequencies, that shall be put as f in the formula.
Re: What is a "low impedance" DRSSTC? More theory
Uspring, Fri May 30 2014, 09:25AM
Solving for the zcs frequencies algebraically seems very nasty, mountains of equations. My computer algebra program went into an endless loop.
Some general features are:
At light loads, high Qsec, there are 2 frequencies near the poles and a center one near the secondary resonance.
At heavy loads, i.e. Qsec lower than 1/k, there is one frequency left near the primary resonance.
A bit about this is here
Uspring, Fri May 30 2014, 09:25AM
Solving for the zcs frequencies algebraically seems very nasty, mountains of equations. My computer algebra program went into an endless loop.
Some general features are:
At light loads, high Qsec, there are 2 frequencies near the poles and a center one near the secondary resonance.
At heavy loads, i.e. Qsec lower than 1/k, there is one frequency left near the primary resonance.
A bit about this is here
Re: What is a "low impedance" DRSSTC? More theory
Steve Conner, Fri May 30 2014, 09:32AM
Very interesting. I'm starting to suspect that as we drive DRSSTC resonators harder, and try to push the ratio of spark length to secondary length as far as it can go, we run into these "heavy load" conditions and this will be the ultimate limit to performance.
This would explain why the recent experiments with "secondary MMCs" worked so well: it allows a physically small resonator to have a lower impedance, thus it can support a bigger spark before its loaded Q drops below 1/k. It also explains why tighter coupling improves performance.
So, I am interested in what the driver (PLL or otherwise) does as the streamer load develops from "light" to "heavy" over the course of the burst. I've also tried solving algebraically for the ZCS frequencies and got nowhere.
With a ground strike, it can go beyond "heavy" and more or less short the secondary out, causing the primary Q to rise above 1/k again.
BTW: Is it (even approximately) true that a loaded Q of 1/k represents a maximum for power transfer? All of this theory is pointing in the direction that we should maybe design our coils to have primary and secondary loaded Qs both equal to (or somewhat greater than) 1/k when they are putting out the design spark length.
This would even give a result similar to Antonio's Butterworth filter design method, if you started out with a similar value of k to what he assumed, but I think k should just be as high as possible without risk of flashovers. If my theory is correct, then the tighter the coupling, the lower the primary loaded Q needs to be, so the less money you need to spend on tank capacitors.
Steve Conner, Fri May 30 2014, 09:32AM
Very interesting.
I'm starting to suspect that as we drive DRSSTC resonators harder, and try to push the ratio of spark length to secondary length as far as it can go, we run into these "heavy load" conditions and this will be the ultimate limit to performance.This would explain why the recent experiments with "secondary MMCs" worked so well: it allows a physically small resonator to have a lower impedance, thus it can support a bigger spark before its loaded Q drops below 1/k. It also explains why tighter coupling improves performance.
So, I am interested in what the driver (PLL or otherwise) does as the streamer load develops from "light" to "heavy" over the course of the burst. I've also tried solving algebraically for the ZCS frequencies and got nowhere.
With a ground strike, it can go beyond "heavy" and more or less short the secondary out, causing the primary Q to rise above 1/k again.
BTW: Is it (even approximately) true that a loaded Q of 1/k represents a maximum for power transfer? All of this theory is pointing in the direction that we should maybe design our coils to have primary and secondary loaded Qs both equal to (or somewhat greater than) 1/k when they are putting out the design spark length.
This would even give a result similar to Antonio's Butterworth filter design method, if you started out with a similar value of k to what he assumed, but I think k should just be as high as possible without risk of flashovers. If my theory is correct, then the tighter the coupling, the lower the primary loaded Q needs to be, so the less money you need to spend on tank capacitors.
Re: What is a "low impedance" DRSSTC? More theory
Uspring, Fri May 30 2014, 01:23PM
When you look at the equation for Qpri
Qpri = (Qsec/k^2) * (1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec),
which is reasonably accurate for the sake of this argument, you'll see, that the first term can be close to 0 if the secondary resonance drops to the primary resonance, at which the coil will run.
The second term 1/(k^2 * Qsec) will become dominant. That does not have to be a problem, if the inverter is matched to it at the point of greatest arc length.
Uspring, Fri May 30 2014, 01:23PM
BTW: Is it (even approximately) true that a loaded Q of 1/k represents a maximum for power transfer?The loaded Q just tells you, how many cycles it takes to ramp up to Iocd. Perhaps you meant Qpri. I don't believe that Qsec = 1/k is necessarily a limit. A PLL, that can lock onto the primary resonance frequency, which is the only zcs f left, will continue with zcs. That involves a jump in operating frequency, which can be large if the coil was ramped up on the center f or the upper pole.
When you look at the equation for Qpri
Qpri = (Qsec/k^2) * (1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec),
which is reasonably accurate for the sake of this argument, you'll see, that the first term can be close to 0 if the secondary resonance drops to the primary resonance, at which the coil will run.
The second term 1/(k^2 * Qsec) will become dominant. That does not have to be a problem, if the inverter is matched to it at the point of greatest arc length.
Re: What is a "low impedance" DRSSTC? More theory
Steve Conner, Fri May 30 2014, 01:33PM
Yes. My question is what will happen to the power output of the coil under these conditions. Assume the driver stays locked to the ZCS frequency and maintains the primary current at the OCD value (by adjusting its average output voltage through pulse skipping, or prematurely ending the burst, which is more or less the same thing for the purposes of this discussion)
As the secondary Q falls below 1/k under heavier and heavier streamer loading, will the power output into the streamer load keep increasing? Or does it go through a maximum at Q=1/k? I feel that it must, but I can't prove it.
Steve Conner, Fri May 30 2014, 01:33PM
Uspring wrote ...
I don't believe that Qsec = 1/k is necessarily a limit. A PLL, that can lock onto the primary resonance frequency, which is the only zcs f left, will continue with zcs...
The second term 1/(k^2 * Qsec) will become dominant. That does not have to be a problem, if the inverter is matched to it at the point of greatest arc length.
I don't believe that Qsec = 1/k is necessarily a limit. A PLL, that can lock onto the primary resonance frequency, which is the only zcs f left, will continue with zcs...
The second term 1/(k^2 * Qsec) will become dominant. That does not have to be a problem, if the inverter is matched to it at the point of greatest arc length.
Yes. My question is what will happen to the power output of the coil under these conditions. Assume the driver stays locked to the ZCS frequency and maintains the primary current at the OCD value (by adjusting its average output voltage through pulse skipping, or prematurely ending the burst, which is more or less the same thing for the purposes of this discussion)
As the secondary Q falls below 1/k under heavier and heavier streamer loading, will the power output into the streamer load keep increasing? Or does it go through a maximum at Q=1/k? I feel that it must, but I can't prove it.
Re: What is a "low impedance" DRSSTC? More theory
Uspring, Fri May 30 2014, 02:29PM
At the point Qpri starts to increase due to the second term, the driver will start to pulse skip to keep the primary current within bounds. This will limit output power. Within the (steady state) model we've assumed the coil itself to be lossless, so input power is equal to output power, i.e.
1/2 * 4/pi * Vbus * Ipri.
Edit: What also can happen (e.g. my coil):
If Qpri gets too low at some point, Ipri might be reduced to a value that prevents arc growth.
Uspring, Fri May 30 2014, 02:29PM
At the point Qpri starts to increase due to the second term, the driver will start to pulse skip to keep the primary current within bounds. This will limit output power. Within the (steady state) model we've assumed the coil itself to be lossless, so input power is equal to output power, i.e.
1/2 * 4/pi * Vbus * Ipri.
Edit: What also can happen (e.g. my coil):
If Qpri gets too low at some point, Ipri might be reduced to a value that prevents arc growth.
Re: What is a "low impedance" DRSSTC? More theory
Dr. Dark Current, Wed Jun 04 2014, 01:50PM
Not having the time now to read the whole thread, but I definitely will, as this is an interesting subject for me.
Just some of my observations (mainly from more "QCW-like" coils, so might not be 100% true for dynamic behavior in a DRSSTC pulse):
The tank circuit in a series-resonant coil (either single-resonant SSTC or dual resonant SSTC) seems to behave like a constant current sink in a steady state. The coil will not spark much if the current is below the "current sink" value, even if it is close. The required current is defined by the "volts per turn" of the primary winding. The Q of the primary tank is not constant. If you design the tank circuit for half surge impedance (2x lower L and 2x higher C), the Q will be about sqrt(2) times lower. For a given set of coils, it is almost inversely proportional to bridge output voltage.
These were just my observations. That said, the peak Q of a DRSSTC primary tank circuit usually seems to be around 10 and you must design the LC circuit according to that. If you set your current limit to a Q of 2-3, the coil will not do much, even if the current is high.
Also, I like to view the Q as a ratio of tank circuit voltage vs. bridge output voltage (average values). This makes it easy to calculate the coils and peak currents.
Dr. Dark Current, Wed Jun 04 2014, 01:50PM
Not having the time now to read the whole thread, but I definitely will, as this is an interesting subject for me.
Just some of my observations (mainly from more "QCW-like" coils, so might not be 100% true for dynamic behavior in a DRSSTC pulse):
The tank circuit in a series-resonant coil (either single-resonant SSTC or dual resonant SSTC) seems to behave like a constant current sink in a steady state. The coil will not spark much if the current is below the "current sink" value, even if it is close. The required current is defined by the "volts per turn" of the primary winding. The Q of the primary tank is not constant. If you design the tank circuit for half surge impedance (2x lower L and 2x higher C), the Q will be about sqrt(2) times lower. For a given set of coils, it is almost inversely proportional to bridge output voltage.
These were just my observations. That said, the peak Q of a DRSSTC primary tank circuit usually seems to be around 10 and you must design the LC circuit according to that. If you set your current limit to a Q of 2-3, the coil will not do much, even if the current is high.
Also, I like to view the Q as a ratio of tank circuit voltage vs. bridge output voltage (average values). This makes it easy to calculate the coils and peak currents.
Re: What is a "low impedance" DRSSTC? More theory
Steve Conner, Wed Jun 04 2014, 02:12PM
Interesting. We know the discharge acts as a (somewhat soggy) voltage clamp, so this implies that an impedance inversion took place somewhere to turn it into a current sink.
This seems plausible, except that it's the opposite of what Antonio's theory predicts. He says the Tesla coil looks like an ideal transformer within its passband, and the voltage stepup ratio is constant, so a voltage clamp at the output should look like a voltage clamp at the input.
I think Uspring's analysis suggests that there could either be an impedance inversion or not, depending on the tuning and operating mode. His equation for Qpri contains both Qsec and 1/Qsec.
If there is an impedance inversion, then in the pulse skipping mode we have a current source driving a current sink, so the duty cycle, output voltage and spark length would be practically undefined.
Steve Conner, Wed Jun 04 2014, 02:12PM
Interesting. We know the discharge acts as a (somewhat soggy) voltage clamp, so this implies that an impedance inversion took place somewhere to turn it into a current sink.
This seems plausible, except that it's the opposite of what Antonio's theory predicts. He says the Tesla coil looks like an ideal transformer within its passband, and the voltage stepup ratio is constant, so a voltage clamp at the output should look like a voltage clamp at the input.
I think Uspring's analysis suggests that there could either be an impedance inversion or not, depending on the tuning and operating mode. His equation for Qpri contains both Qsec and 1/Qsec.
If there is an impedance inversion, then in the pulse skipping mode we have a current source driving a current sink, so the duty cycle, output voltage and spark length would be practically undefined.
Re: What is a "low impedance" DRSSTC? More theory
Dr. Dark Current, Wed Jun 04 2014, 02:34PM
Steve, yes it does work as a transformer and it does transform the voltage clamp, but most likely only in "DRSSTC" mode. If the voltage on the primary is constant, the current through the tank capacitor is constant, this is where the "voltage to current conversion" happens - on the reactance of the tank cap.
Dr. Dark Current, Wed Jun 04 2014, 02:34PM
Steve, yes it does work as a transformer and it does transform the voltage clamp, but most likely only in "DRSSTC" mode. If the voltage on the primary is constant, the current through the tank capacitor is constant, this is where the "voltage to current conversion" happens - on the reactance of the tank cap.
Re: What is a "low impedance" DRSSTC? More theory
Uspring, Wed Jun 04 2014, 05:27PM
Dr. DC:
The equation for Qpri is derived under a steady state assumption. It should work better for QCWs than for DRSSTCs.
A hard arc voltage clamp and constant primary current behaviour implies Qpri being proportional to Qsec. This can be accomodated by the equation if we assume (for a dual resonant zcs QCW coil):
a) Qsec >> 1/k, which makes the first term dominant
and
b) f/fsec is constant, which keeps the proportionality constant
If the coil is e.g. run at the lower pole the first term
(Qsec/k^2) * (1 - f^2/fsec^2)^2
simplifies to about Qsec, i.e.
Qpri = Qsec (for large Qsec)
QCWs are run at much less (peak) power than DRSSTCs, so the assumption of a large Qsec might hold. It would be interesting to know typical primary currents and voltages of your QCW and the k to check, whether this makes sense.
Edit:
Uspring, Wed Jun 04 2014, 05:27PM
Dr. DC:
The equation for Qpri is derived under a steady state assumption. It should work better for QCWs than for DRSSTCs.
A hard arc voltage clamp and constant primary current behaviour implies Qpri being proportional to Qsec. This can be accomodated by the equation if we assume (for a dual resonant zcs QCW coil):
a) Qsec >> 1/k, which makes the first term dominant
and
b) f/fsec is constant, which keeps the proportionality constant
If the coil is e.g. run at the lower pole the first term
(Qsec/k^2) * (1 - f^2/fsec^2)^2
simplifies to about Qsec, i.e.
Qpri = Qsec (for large Qsec)
QCWs are run at much less (peak) power than DRSSTCs, so the assumption of a large Qsec might hold. It would be interesting to know typical primary currents and voltages of your QCW and the k to check, whether this makes sense.
Edit:
Also, I like to view the Q as a ratio of tank circuit voltage vs. bridge output voltage (average values). This makes it easy to calculate the coils and peak currents.Yes, that basically is what Qpri is.
Re: What is a "low impedance" DRSSTC? More theory
Steve Conner, Mon Jun 16 2014, 02:35PM
I think I derived another interesting relation.
A PLL driven coil is at risk from hard switching, because the PLL loop filter takes a finite time to respond to rapid changes in frequency. This can only be speeded up so far before the filter suffers from excessive ripple.
Let's assume the worst case situation where the resonator is suddenly shorted by a ground strike leaving the PLL no time to do anything at all about it.
From our previous steady state arguments, the counter EMF induced in the primary by the resonator must be (roughly) equal to the output voltage of the bridge. If the resonator is shorted, this counter EMF will disappear almost instantly. The primary current can't change instantaneously because of the inductance of the primary coil, but its rate of change will change, so it will pass through zero at a different time from what the PLL expects based on previous zero crossings.
From (insert bunch of calculus and trig here ) I think it then follows that the worst case hard-switching current you can possibly encounter is equal to Ipk/Qpri.
If this is true then for the usual designs of DRSSTCs, the resulting current should be within the switching SOA of the kinds of IGBTs normally used. The hard switching may cause increased losses but it shouldn't blow anything up instantly due to latchup or transient overvoltage.
Steve Conner, Mon Jun 16 2014, 02:35PM
I think I derived another interesting relation.
A PLL driven coil is at risk from hard switching, because the PLL loop filter takes a finite time to respond to rapid changes in frequency. This can only be speeded up so far before the filter suffers from excessive ripple.
Let's assume the worst case situation where the resonator is suddenly shorted by a ground strike leaving the PLL no time to do anything at all about it.
From our previous steady state arguments, the counter EMF induced in the primary by the resonator must be (roughly) equal to the output voltage of the bridge. If the resonator is shorted, this counter EMF will disappear almost instantly. The primary current can't change instantaneously because of the inductance of the primary coil, but its rate of change will change, so it will pass through zero at a different time from what the PLL expects based on previous zero crossings.
From (insert bunch of calculus and trig here
) I think it then follows that the worst case hard-switching current you can possibly encounter is equal to Ipk/Qpri.If this is true then for the usual designs of DRSSTCs, the resulting current should be within the switching SOA of the kinds of IGBTs normally used. The hard switching may cause increased losses but it shouldn't blow anything up instantly due to latchup or transient overvoltage.
Re: What is a "low impedance" DRSSTC? More theory
Uspring, Tue Jun 17 2014, 10:02AM
That's complicated stuff. A first thought is to think of an equivalent circuit for the primary tank to have a resistor added, which causes the Qpri. That would then be shorted during a ground strike, causing a voltage jump in the primary. Makes my head smoke to derive a phase jump from that.
Also it might be a too simplistic way of deriving a phase jump, since the secondary-primary current phase relation might also have an impact. The zcs frequency, which is not the same as the primary res frequency, is also dependent on the secondary. You've probably figured all that, I haven't
For a DRSSTC switching by primary current info via CT, that shouldn't be an issue.
Uspring, Tue Jun 17 2014, 10:02AM
That's complicated stuff. A first thought is to think of an equivalent circuit for the primary tank to have a resistor added, which causes the Qpri. That would then be shorted during a ground strike, causing a voltage jump in the primary. Makes my head smoke to derive a phase jump from that.
Also it might be a too simplistic way of deriving a phase jump, since the secondary-primary current phase relation might also have an impact. The zcs frequency, which is not the same as the primary res frequency, is also dependent on the secondary. You've probably figured all that, I haven't
For a DRSSTC switching by primary current info via CT, that shouldn't be an issue.
Re: What is a "low impedance" DRSSTC? More theory
Steve Conner, Tue Jun 17 2014, 11:08AM
Yes, I don't have a formal proof to go in the (insert bunch of calculus) slot yet
But my argument is based on things happening on a time scale of less than 1/2 cycle, so the separate resonant modes and Qs can be ignored as these are steady state things that only make sense in the context of multiple cycles. It basically reduces to a jump in voltage across an inductor.
Steve Conner, Tue Jun 17 2014, 11:08AM
Yes, I don't have a formal proof to go in the (insert bunch of calculus) slot yet
But my argument is based on things happening on a time scale of less than 1/2 cycle, so the separate resonant modes and Qs can be ignored as these are steady state things that only make sense in the context of multiple cycles. It basically reduces to a jump in voltage across an inductor.
Re: What is a "low impedance" DRSSTC? More theory
Antonio, Sat Jun 21 2014, 01:52AM
I made some calculations here, ignoring losses. If a drsstc has its output short-circuited after some time (with the short-circuit lasting for several cycles), the input current becomes limited only by the primary circuit, with the secondary inductance reflected to it. As the driving frequency is at approximately the resonance frequency of the resulting LC tank (it is exactly this with the Butterworth filter design), the input current goes up with a ramp envelope, starting from its initial value and increasing by the same amount at each cycle. This amount is 4*V*sqrt(Ca/(La(1-k^2))), where V is the peak voltage of the square-wave driver.
Antonio, Sat Jun 21 2014, 01:52AM
I made some calculations here, ignoring losses. If a drsstc has its output short-circuited after some time (with the short-circuit lasting for several cycles), the input current becomes limited only by the primary circuit, with the secondary inductance reflected to it. As the driving frequency is at approximately the resonance frequency of the resulting LC tank (it is exactly this with the Butterworth filter design), the input current goes up with a ramp envelope, starting from its initial value and increasing by the same amount at each cycle. This amount is 4*V*sqrt(Ca/(La(1-k^2))), where V is the peak voltage of the square-wave driver.
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