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Driving 'Fiddy's Flybacks' in flyback mode.

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LAN_403

Fiddy

Mon Nov 17 2014, 08:01AM

Registered Member #8817 Joined: Mon Dec 17 2012, 05:16AM
Location: Australia
Posts: 110

I use eagle cad for the boards i make, it has a schematic drawing part to it

this is what eagle cad schematic looks like:

Headamp Supply Sch

Ash Small

Mon Nov 17 2014, 08:48AM

Registered Member #3414 Joined: Sun Nov 14 2010, 05:05PM
Location: UK
Posts: 4245

I really like the look of this setup, it's so simple, and gives a REALLY fast turn off because the PNP bipolar transistor never saturates, but I do have a few questions about it.

1416076925 3414 FT1630 Pnp Turn Off Circuit

Firstly, most of the diagrams in the App note it came from are pretty much complete, so I have to assume that this is, however, pretty much all the PNP datasheets I've looked at say max voltage between Emitter and Base can't exceed five volts, yet most MOSFET data sheets say they need more than this, so the question is this:

As it is, assuming the output from the 556 is 12V, when the MOSFET is on, Veb will be equal to the diode forward voltage drop, but when the MOSFET turns off, at first impression, it looks like Veb is 12V. Is this actually the case, OR, once the PNP BJT starts to conduct, does the voltage on the Gate of the MOSFET drop to an acceptable voltage OR due to the fact that there is only ~250nC of charge on the Gate, does this mean it doesn't matter OR is there some other explanation?

I've been up all night puzzling over this, but can find very little information on the internet regarding PNP 'switch off' transistors.

EDIT: Does the Gate 'mesh' resistance play a part here, and keep Veb under 5V? (I'm just guessing here)

EDIT: the other advantage of this setup is it reduces the current flowing in and out of the 555 by half.

Another advantage is it eliminates 'ground bounce', whatever that is

Dr. Dark Current

Mon Nov 17 2014, 09:45AM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

At the frequencies of interest (few tens of kHz), the 555/556 has more than enough current to drive a powerful MOSFET. No additional circuitry needed.

Ash Small

Mon Nov 17 2014, 11:31AM

Registered Member #3414 Joined: Sun Nov 14 2010, 05:05PM
Location: UK
Posts: 4245

Dr. Dark Current wrote ...

At the frequencies of interest (few tens of kHz), the 555/556 has more than enough current to drive a powerful MOSFET. No additional circuitry needed.

But the sbove setup gives faster 'turn off', according to the app note I posted above, as the MOSFET doesn't need to discharge through the gate resistor, and everything I've read says you want as fast a turn off as possible for 'flyback topology'.

It's also the same 'parts count' as just discharging through the gate resistor, because that entails adding two Shottkys, one from GND to 'out' and one from 'out' to Vcc, to protect the output transistors in the 555.

Steve Conner

Mon Nov 17 2014, 12:37PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

The local turnoff circuit doesn't protect the 555 output transistors in any way, so if you needed protection diodes before, you would still need them.

Veb of the turnoff transistor can never be exceeded. In the forward direction, it will clamp the voltage itself by conducting through its own base-emitter junction. In the reverse direction, the diode conducts and clamps Veb to 0.7V.

Too fast turnoff can be as bad as too slow sometimes. Search the archives for a thread called "Goldilocks Gate Drive"

Ash Small

Mon Nov 17 2014, 01:23PM

Registered Member #3414 Joined: Sun Nov 14 2010, 05:05PM
Location: UK
Posts: 4245

Steve Conner wrote ...

The local turnoff circuit doesn't protect the 555 output transistors in any way, so if you needed protection diodes before, you would still need them.

The application note linked to above states that the local turn off circuit eliminates 'ground bounce', which, according to Wikipedia is

"In electronic engineering, ground bounce is a phenomenon associated with transistor switching where the gate voltage can appear to be less than the local ground potential, causing the unstable operation of a logic gate.

Ground bounce is usually seen on high density VLSI where insufficient precautions have been taken to supply a logic gate with a sufficiently low resistance connection (or sufficiently high capacitance) to ground. In this phenomenon, when the gate is turned on, enough current flows through the emitter-collector circuit that the silicon in the immediate vicinity of the emitter is pulled high, sometimes by several volts, thus raising the local ground, as perceived by the transistor, to a value significantly above true ground. Relative to this local ground, the BASE voltage can go negative, thus shutting off the transistor. As the excess local charge dissipates, the transistor turns back on, possibly causing a repeat of the phenomenon, sometimes up to a half-dozen bounces."

Which appears to be, from what I can make out, the reason why the extra protection is required in other setups, eg just using a gate resistor, but I will re-read it.

I'm no expert, though, hence the reason for the question.

Thanks for the other info. I'll look it up.

I have been doing a lot of Googling about gate drive systems. I do want to 'keep it simple' though, but leave room on the board for possible modification in the future.

EDIT: The discharge rate is still limited by the Gate 'mesh' resistance. It's this that defines the 'switching time' in the first place, along with the gate capacitance (RC time constant).

EDIT: This Fairchild App note on 'Ground Bounce' states that

" In order to change the output from a HIGH to a LOW, current
must flow to discharge the load capacitance. This current,
as it changes, causes a voltage to be generated
across the inductances in the circuit. The formula for the
voltage across an inductor is V = L â€¢ (Î”I/Î”t). This induced
voltage creates what is known as ground bounce."

As the current doesn't flow back to the driver chip, but goes to ground instead via the PNP BJT, the above circuit supposedly eliminates it. I'm still reading the full article, though.

EDIT: The 'Fairchild App note' also says this

"Although this discussion is limited to ground bounce generated
during HIGH-to-LOW transitions, it should be noted
that the ground bounce is also generated during LOW-to-
HIGH transitions. This ground bounce is created by the
large gate capacitances associated with the output transistors
on the die. Because these gate capacitances are
larger than the gate capacitances of earlier-stage transistors,
more current is generated when they switch. The output
buffer stages of CMOS devices are inverters; thus their
inputs are switching HIGH-to-LOW when their outputs are
switching LOW-to-HIGH. It is the currents associated with
switching these inputs to the output transistors that generate
ground bounce when the outputs switch LOW-to-HIGH.
This LOW-to-HIGH ground bounce has a much smaller
amplitude and therefore does not present the same concern."

The 'TI' App note from which the 'local PNP turnoff' diagram was taken suggests using Shottkys, one from GND to 'out' and one fron 'out' to Vcc to deal with ground bounce, and implies that they aren't needed for the 'local PNP turnoff' setup, although it still recommends using capacitors.

Patrick

Mon Nov 17 2014, 10:19PM

Registered Member #2431 Joined: Tue Oct 13 2009, 09:47PM
Location: Chico, CA. USA
Posts: 5639

Ash Small wrote ...

Ground bounce is usually seen on high density VLSI where insufficient precautions have been taken to supply a logic gate with a sufficiently low resistance connection (or sufficiently high capacitance) to ground.

Is this the only reason, or one of several for why we see capacitor infantry lined up near CPUs ?

Ash Small

Mon Nov 17 2014, 10:24PM

Registered Member #3414 Joined: Sun Nov 14 2010, 05:05PM
Location: UK
Posts: 4245

Patrick wrote ...

Is this the only reason, or one of several for why we see capacitor infantry lined up near CPUs ?

There are other reasons for the capacitors. I've been reading up on DIY reflowi soldering ( google 'Skillet reflow'), and looking at SMD's, but I'm not sure I need the Schottkys that the TI App note recommends for 'ground bounce'.

EDIT: just to qualify the above statement, if using the 'local PNP switch off' setup, which is supposed to eliminate ground bounce, the schottkys may not be required, but for other setups, eg just using an output resistor or totem pole then the it would be advisable to use the shottkys.

Shrad

Tue Nov 18 2014, 08:20AM

Registered Member #3215 Joined: Sun Sept 19 2010, 08:42PM
Location:
Posts: 780

I guess that those schottkys are inside the silicon for most IO now, and capacitors taking much more space, they haven't been able to integrate them yet

Sigurthr

Tue Nov 18 2014, 04:51PM

Registered Member #4463 Joined: Wed Apr 18 2012, 08:08AM
Location: MI's Upper Peninsula
Posts: 597

There's a lot more to it than miniaturization. A lot of it is balancing high frequency impedances with parasitics.

For the task at hand I still think it isn't really needed to have secondary active turn off switching. If you're that concerned just run the 555 on 15v and use a BJT totem pole to switch the fet gate. You'll get fast turn off and still have 10v on the gate. I'm working on debugging a buddy's board now that uses this setup and was hard switching a power fet at 2.2MHz. The drive section didn't break a sweat.

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