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Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
GeordieBoy wrote ...
Perhaps a similar approach should be adopted for peak current rating of IGBTs in DRSSTCs too!
Richie and I have been saying this for years, look in the forum archives for our arguments! To summarize: If the manufacturer thought it would take 4000 amps reliably, he'd use that in his advertising literature: "Best-in-class pulse current capability"! Of course, a Chevy engine was never designed to put out 4000hp reliably either, but that doesn't stop drag racers. You basically have to decide whether you're driving your IGBTs to the store to get groceries, or drag racing them, in which case don't be too surprised if they throw a rod clean through the crankcase, so to speak.
Having said that, I've seen Richie running 500V MOSFETs off a 499V DC bus. When I asked him if that was safe, he turned it up to 501!
I also want to mention that I've never liked this N/P channel MOSFET circuit, I think it's straight outa the ghetto! You can tweak it to make it work, but MOSFET threshold voltages change wildly with temperature, so you can't guarantee that it'll continue working. I've never seen any way of driving the P-channel highside device that didn't just look like a hack. When I went to make isolated gate drivers for my abandoned Odin project, I used two N-channel devices driven by a little GDT.
A certain amount of shoot-through is sometimes tolerated in the interests of speed. The 555 timer's output stage is famous for it (the datasheet even admits it) and 4000 series CMOS also do it on 15V. That's why you must never leave unused inputs floating: if they get into the linear region, both MOSFETs in the output buffer turn on at once, and they burn up.
Registered Member #205
Joined: Sat Feb 18 2006, 11:59AM
Location: Skørping, Denmark
Posts: 741
Steve, Richie
I dont think anyone in their right mind are questioning your collective judgement regarding silicon durability. Datasheets specify pulse currents to 50Hz, so obviously there is headroom, but for the reasons you mention, there is little incentive to advertise shorter pulses. Like Richie said @ one meeting in Canbridge: "If you violate specksheet ratings, you are on your own!".
This is true, but on the other side, I have built Museum coils that operate CM600´s into the thousands of amperes for years on end, so I for one feel quite comfortable being on my own there.
Anyway, now that it has been made official that my gate driver totem pole is a _HACK_, let me say that the best reason I have for liking the PNP/NPN output is that I understand it. If I could understand your gate driver, from Odin, I might have a go at it, although it contains 3 transistors and a dual output winding gate transformer.
I would appreciate it, if you walk us through the circuit and tell us how it works.
Registered Member #289
Joined: Mon Mar 06 2006, 10:45AM
Location: Conroe, TX
Posts: 154
Finn Hammer wrote ...
The video showed a current sweep from 50A to 500A.
About gate drive: I am having a very hard time justifying my initial desicion to use opto's and separate gate drivers, when it would be so much simpler to build a nice little semi-high voltage bridge, and drive a step down gate drive transformer. It is no easy task to configure the totem pole output stage of the driver and get both zero shoot trough as well as high current output ability: When I slow down the turn on enough to keep shoot trough low, the turn on is prolonged so that the ability to deliver current within the time frame of turning on of the IGBT is impaired. I will try the old trick with zeners on the gate, which you may recall from the days of the beefy driver.
(didn'd help)
What I _really_ need is a tiny NTC resistor, which could delay the ramp up to miller plateau, then turn low resistance there, to allow fast full turn on.
Well, this is fun anyway, and perhaps I should just make that bridge/gate tranny and get on with it.
Thanks for -your- work. It was the work of pioneers like yourself that got me started.
Cheers, Finn Hammer
I understand the appeal of the totem pole. It's compact, simple, and easy to build. It's not quite that simple to tweak though Honestly, there are very few applications I can justify not using a GDT in. No floating PS, many KV isolation, nearly impossible to break (although I did blow one up once), bipolar, and they won't cause shoot though in a bridge. I understand what Richie says about leakage slowing things down, but this can be easily designed out. There are commercial GDTs with 600V/uS and higher slew rates available. I think putting 18V on your gate in 30ns (obviously there are other variables here, but you get the point) is probably good enough for most apps
I do use direct gate drive in applications where the duty cycle will be changing very rapidly and/or to a high degree (Class D, etc.). GDTs just don't quite cut it here, IMO.
A dual gate drive IC driving a small GDT, which in turn drives a full bridge of Low Rds ON FETs running off a single 20V rail which is then used to drive a large, well designed GDT, could easily match the speed of an N/P-ch setup when driving a CM600. I have even experimented with the concept of an off-line gate driver. I used this to drive CM1000's in my 16" DRSSTC to make +20' arcs with great results. The only problem was the Fo of 70KHz cause excessive dissipation in the painfully slow CM1000's. I've got another big one in the works, though, with an Fo of ~35KHz to resolve this issue.
I'm glad to see the SS stuff has taken off like it has. This whole SSTC/DRSSTC thing still seems so new to me; it’s funny to think I've been working on it for more than a decade It gets even better when I see people who's first TC EVER is SS. I would have never thought people would consider an SS design over a SG design to cut their teeth on...
Registered Member #205
Joined: Sat Feb 18 2006, 11:59AM
Location: Skørping, Denmark
Posts: 741
hvguy wrote ...
A dual gate drive IC driving a small GDT, which in turn drives a full bridge of Low Rds ON FETs running of a single 20V rail which is then used to drive a large, well designed GDT, could easily match the speed of and N/P-ch setup when driving a CM600. I have even experimented with the concept of an off-line gate driver. I used this to drive CM1000's in my 16" DRSSTC to make +20' arcs with great results. The only problem was the Fo of 70KHz cause excessive dissipation in the painfully slow CM1000's. I've got another big one is the works though with a Fo of ~35KHz so resolve this issue.
Decisions,Decisions.
Well I am going to the end with this N/P driver, then I'l try that fancy high voltage full bridge driver with step down gate transformers. I have a nice ferrite part here waiting to get planted on a pcb, which could be used to split the signals.
After all, it is simpler that way, trade one full bridge with 4 half bridges.
Registered Member #289
Joined: Mon Mar 06 2006, 10:45AM
Location: Conroe, TX
Posts: 154
Well, you definitely of a ton of options
Steve W.'s "new" driver with a N/P full bridge uses a creative boot strap arrangement that may be worth looking into if you haven't already. Also, as i'm sure you know, finding a good set of matched part numbers helps. There are so many different brands/ratings to chose from it can be hard to find a "good" complementary pair.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Maybe I was a little mean about the N/P circuit. But the one thing I still don't like about it is that the gate driver is referenced to the 0V rail, whereas the gate of the P-FET is referenced to the supply rail. This change of reference means that any noise on the supply rail (ringing from transients etc) could be amplified by the P-FET as if it was gate drive. This is a potential source of instability, so, good decoupling of the supply rail is uber important.
Finn, a good starting point might be to put capacitors across those zeners. Also, you can have my set of Odin drivers and the power supply to play with if you want them. They were designed to work with my PLL system, but I don't see any reason why they shouldn't work with a Steve Ward driver. Condition, you must rename your coil to Odin The Ball-Thumper
How the circuit works: It's basically a normal half-bridge, except that the low-side MOSFET is driven through an intermediate small FET, which inverts the signal. The phase of the low-side GDT winding is reversed to compensate this inversion.
The reason for this is to make sure that the low-side MOSFET stays on in the absence of any gate drive, clamping the main IGBT securely off. If I just drove both FETs straight from the GDT, then they would both be off in between bursts, leaving the main IGBT gate floating.
As a side benefit, this intermediate stage turns the low-side FET off somewhat faster than it turns it on, which helps to prevent shoot-through.
The diodes D1 and D2 provide two alternate sources of power for this little FET circuit: the main power supply, and a rectified sample of the gate drive. This prevents a spectacular failure mode that I found: if the power supply fails but the gate drive continues, then the high-side FET carries on working, but the low-side one dies. The result is that all four main IGBTs got turned on at once.
Registered Member #1232
Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881
The "step-down" GDT drive method is a very good technique for driving highly capacitive devices, (or parallel combinations of devices.)
It is particularly effective when the GDT is placed very close to the IGBT brick / MOSFETs being driven. The transformation property of the GDT steps down the drive voltage but steps up the drive current by the same ratio. This means that you can get lots of amps available right at the device's gate terminal. It transforms the gate impedance by the square of the turns ratio. Meaning that if you have an 8nF Cg device and a 4:1 GDT, the effective capacitance seen at the drive side is only 500pF.
A drive circuit using the same 4:1 GDT is also 16 times more tolerant of any stray-inductance on the drive side (primary) of the GDT than the secondary side. This means that it should be placed right on top of the gates being driven, but longer twisted pairs can be tolerated on the primary side running back to the driver circuitry.
Finally it is worth remembering that lightening fast isn't always best. In general turn-off should be faster than turn-on. This is because when a device turns off the current it was carrying is handed to a diode. Conversely when a device turns on it grabs the load current from a diode. In general diodes are much faster at turning on than they are at turning off. In other words you can usually turn off a MOSFET or IGBT as quickly as possible with little fear that the diode might not turn on fast enough and catch the current. The opposite cannot be said, however. Diodes are slow to turn-off and therefore it is not a good idea to turn on a switch too quickly otherwise there will be a horrendous surge of reverse-recovery current through both devices.
In a DRSSTC circuit there is the added quirk that the load current is sinusoidal. This means that if you switch your devices somewhere close to the zero current crossings things should be less critical in terms of power dissipation. It also means that the device being turned on can be done so at a more leisurely pace. As the load current rises the device only needs to be turned on sufficiently to support the instantaneous load current that is flowing. As time passes and the sinewave load current builds, then the device needs to be enhanced futher and further to prevent de-saturation.
Getting this turn-on rate just right gives the holy grail of power electronics:
1. The coolest possible device temperatures 2. The cleanest switching waveforms 3. The minimum of radiated interference
-Richie,
EDIT: I should clarify that direct gate-drive as in Steve C's circuit is better than via a GDT because you have direct control over the gate in terms of rise and fall times and much less stray inductance between the drive circuit and the actual device gate. However, the "step-down" GDT method is better than a normal 1:1 GDT for the reasons discussed.
Registered Member #205
Joined: Sat Feb 18 2006, 11:59AM
Location: Skørping, Denmark
Posts: 741
Steve McConner wrote ...
Finn, a good starting point might be to put capacitors across those zeners.
I have 330µF sitting less than 10mm (3/8") from the zeners. These are of course referenced to the groundplane on top of the board. Then the Opto has 2 x 100nF each going from rails to ground plane, with only 2,54mm (1/10") from supply pins to caps.. Finally, the source legs of poth MosFets each have a 47µF low esr surface mount tantalum, again referenced to ground and never more than 5mm from the pins. Pcb is 105µ, so able to carry current. Does that bypass scheme sound reasonable to you?
Steve McConner wrote ...
Also, you can have my set of Odin drivers and the power supply to play with if you want them. They were designed to work with my PLL system, but I don't see any reason why they shouldn't work with a Steve Ward driver. Condition, you must rename your coil to Odin The Ball-Thumper
That is a sweet offer, and I hope you will leave it open for later. Reason: I have to learn from any mistakes I make. If this coil fails, then I'd love to make Odin come true. Only condition: Since you hurt me so, with the ghetto remarks (here where I thought I was being elegant) The coils name is Odin the Ghetto Blaster. It's a good name and about time to name good Ole Odin something contemporary. They weren't whimps, those old gods.
Steve McConner wrote ...
How the circuit works: It's basically a normal half-bridge, except that the low-side MOSFET is driven through an intermediate small FET, which inverts the signal. The phase of the low-side GDT winding is reversed to compensate this inversion.
The reason for this is to make sure that the low-side MOSFET stays on in the absence of any gate drive, clamping the main IGBT securely off. If I just drove both FETs straight from the GDT, then they would both be off in between bursts, leaving the main IGBT gate floating.
As a side benefit, this intermediate stage turns the low-side FET off somewhat faster than it turns it on, which helps to prevent shoot-through.
The diodes D1 and D2 provide two alternate sources of power for this little FET circuit: the main power supply, and a rectified sample of the gate drive. This prevents a spectacular failure mode that I found: if the power supply fails but the gate drive continues, then the high-side FET carries on working, but the low-side one dies. The result is that all four main IGBTs got turned on at once.
More discussion of this driver here:
Thanks for that explanation. It was in particular the 2 diodes and the 100nF cap that had me puzzeled.
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"Thumper"
To summarize: If the manufacturer thought it would take 4000 amps reliably, he'd use that in his advertising literature: "Best-in-class pulse current capability"! Of course, a Chevy engine was never designed to put out 4000hp reliably either, but that doesn't stop drag racers. You basically have to decide whether you're driving your IGBTs to the store to get groceries, or drag racing them, in which case don't be too surprised if they throw a rod clean through the crankcase, so to speak.
It gets even better when I see people who's first TC EVER is SS. I would have never thought people would consider an SS design over a SG design to cut their teeth on...
