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Dinges

Sun Jan 31 2010, 09:32PM

Registered Member #2511 Joined: Mon Dec 07 2009, 02:46AM
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wrote ...
Maybe your deadtime between switching is too long?

Could that explain why the dirt only occurs at off-resonance frequencies?

One other thing I noticed is that the noise in the valleys is much more noticeable than in the hills.

Will have to scope the inverter waveshape tomorrow, that may provide more clues; just realized that tank-voltage is not really relevant, but it just happened I was looking at the tank waveshape when I was using the induction heater. Will be interesting to see what's actually happening to the inverter waveshape.

wrote ...
I am not knowledgeable enough to tell. How do you control your switch timing?

Switch timing is controlled by the PLL - it takes one input signal for the phase comparator from the tank capacitor (tank voltage), and the other one from the inverter (an extra single-turn winding over the coupling transformer), thereby cancelling any phase-errors that you'd get by sampling the tank voltage (one input for the phase comparator) and connecting the other input (pin 3 of the 4046) straight to the VCO output (pin 4 of the 4046). Any timing delays in the gatedriver and inverter get translated into phase errors and off-resonance locking, I think.

I had a lot of problems earlier with the circuit - I think there was too much phase delay between the two signals, due to different delay times (extra inverters, etc.). After solving that one, it locked properly. I haven't added any manually tunable phase delays (RC-filters) to deliberately slow one of the two phase comparator signals down, to tune to slightly above resonance, instead of exactly on resonance.

wrote ...
What is the frequency range of your PLL?

Frequency range is from 115-155 kHz, with VCO voltage at 0 and 15V, respectively.

wrote ...
What happens if you put something other than a bolt inside like a chunk of copper or a small steel nut?

It locks and starts heating. Have tried larger pieces of steel, copper pipe (which got barely lukewarm - but the tank coil got very hot) and aluminium pipe (which got nicely warm; resonant frequency with the aluminium workpiece had actually risen by about 15 kHz, to my surprize: was resonant at about 150 kHz.)

wrote ...
I found with my topology it locks onto resonance, but is usually a little off and needs to get perfectly tuned by adjusting a pot to my integrator feedback loop.

It seems to be pretty good on frequency, as far as I can tell. No fiddling of any sort required.

One thing that surprized me is that by adjusting the power control knob (which detunes the VCO to a higher frequency) has less effect than I expected. Don't get me wrong, I can reduce output perfectly well to safe levels (~100W) by detuning, but I had expected 1-2 kHz difference to have a lot of effect; in practice, the difference is smaller than I'd expect. Maybe the Q (quality factor) of my tank circuit is lower than yours?

Then again, with a load in it, the difference in loaded Q is probably negligeable?

wrote ...
As soon I have learned enough I am going to build an 8kw unit using a microprocessor to lock onto resonance using a PLL/VCO. I am hoping to have resolution down to 50hz increments for scaning a frequency range of 50-150khz.

Sounds like an interesting project that I'd follow with much interest.

Peter.

Dinges

Sun Jan 31 2010, 09:39PM

Registered Member #2511 Joined: Mon Dec 07 2009, 02:46AM
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Steve McConner wrote ...
The dirt is just switching transients. Above resonance, the FETs don't switch at zero current any more, so they start to make these little bursts of RF as they suddenly interrupt this non-zero current.

Ok, I see. That actually makes good sense. Am reassured now.

wrote ...
It's not a problem. If it looked like this -that might be a problem

Yikes! And here I was worrying....

Thanks for clarifying, Steve.

Peter.

GeordieBoy

Sun Jan 31 2010, 09:42PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
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Posts: 881

As Steve Conner said, those tiny little bits of ringing on the tank voltage waveform are nothing to worry about.

When operating above resonance, the load current abruptly switches from the MOSFET which is turning off to the FWD across the opposite MOSFET before that device turns on.

This "commutation" results in a relatively sharp slew of the voltage from one rail (for instance the bottom supply rail) when the bottom MOSFET is on, to the top rail when the FWD catches the load current and clamps it to the supply. It is this high dv/dt that causes the ringing in VHF range.

Don't worry about it though it is perfectly normal! (If you really wanted to go for a low EMI design to meet approvals you would put lossless snubber capacitors across the MOSFETs and increase the dead-time to control the dv/dt during the commutation time!)

It's really not necessary though

As long as you operate in the ZVS region above resonance you won't get the horrendous reverse-recovery ringing!

-Richie,

IamSmooth

Sun Jan 31 2010, 11:11PM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
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If you look at this page in the middle

you will see the transition from ModeIII to ModeIV, which Richie is talking about. It is the transition from one supply rail to the next. I believe I got this image from one of his references. Thanks Richie.

Dinges, you mentioned that you are looking at the cap-tank voltage and what other waveform? Try looking at the inverter voltage and inverter current simultaneously. This will be make it easier to see how close you are to true zero-crossing. When it is dead-on you will have the most power. I keep it just a little bit higher than resonance.

GeordieBoy

Mon Feb 01 2010, 02:03PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
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Posts: 881

> ...you will see the transition from ModeIII to ModeIV, which Richie is talking about. It is the transition from one supply rail to the next.

If you take the switch capacitances into account (or put additional caps across the switches) then the inverter actually has 6 switching phases (or modes as you call them) instead of 4.

They would be as follows:

1. Load current flows down through top IGBT channel,
2. Load current charges top cap, and discharges bottom capacitor,
(This capacitor charging action is what slews the output voltage from the top rail to the bottom rail during the deadtime,)
3. Load current flows up through bottom diode,
(Output is now clamped to negative supply rail.)
4. Load current flows down through bottom IGBT channel,
5. Load current charges bottom cap, and discharges top capacitor,
(This capacitor charging action is what slews the output voltage from the bottom rail to the top rail during the deadtime,)
6. Load current flows up through top diode,
(Output is now clamped to positive supply rail.)

It is the inductive load current freewheeling during the dead-time that actually drives the mid-point of the inverter smoothly from one supply rail to the other.

When this is working optimally you get a nice clean trapezoidal output voltage waveform from the inverter where the slopes of the rising and falling edges are quite noticeable. The relatively low slew rate massively reduces EMI generation from the inverter, whilst the ZVS and "turn-off snubbing" from the capacitors achieves very low switching losses indeed.

-Richie,

Dinges

Mon Feb 01 2010, 04:18PM

Registered Member #2511 Joined: Mon Dec 07 2009, 02:46AM
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I notice that the 4046 VCO's voltage isn't neatly 7.5 V( middle of supply voltage) which would happen at 90 degree phase difference between the two comparator inputs, but is sometimes below it, at about 5.5V; does this mean that I'm not exactly driving it at resonance? Or are there phase delays somewhere in the signal path? And does this mean that my phase is off by ((7.5V-5.5V)/15V)* 180 deg = 24 degrees?

Either way, it seems to work very nicely. When retuning for *exact* resonance, power throughput hardly increases. Is this because of the low Q of a loaded workcoil? (as opposed to an unloaded coil, which likely has Q's approaching 200)

On another subject: I'm now boxing it all up in a case, but, in the mean time, am pondering a follow-up induction heater project that should go up to about 2.5-3 kW. Already have an old 48V/100A (7.2kVA input) ex-telecom battery charger in 19" rack, which has 8 big MOSFETs (MTE30N50E; 30A, 500V, Rds,on=0.15 ohm, ISOTOP http://www.datasheetcatalog.org/datasheet/motorola/MTE30N50E.pdf) in full-bridge configuration (2 FETs parallel per leg); see pictures below.

(in the picture above the pencil points to the two cooling fins that contain the 8 FETs; below the pencil is one of the two ferrite transformers (with aluminium cooling fins...); to the right of the pencil is the cooling fin with the rectifiers, also ISOTOP); on the rear of the rack are 3 large fans that blow air over the fins, which have been removed for this picture)

I intend to re-use the cabinet and the power-section (with some modifications); saves a lot of the mechanical work. Just add a PLL controller and tank circuit and we're finished.

The questions:

- does a full-bridge configuration offer any advantages over a half-bridge in this configuration?
- how to determine the maximum frequency these FETs can be driven? What determines the upper-frequency limit? Somehow I doubt I can drive these FETs at the same frequency (140kHz) as my present induction heater, or could I?

Peter.

IamSmooth

Mon Feb 01 2010, 04:21PM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
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Richie, is there an optimal capacitance value or will any reasonable value work? I have 1.0uf snubbers. Would 1.5uf be better? If there is an optimal value, how would one calculate it?

ALso, during deadtime both mosfets are off, so how is the capacitor discharging?

Dinges wrote ...

I notice that the 4046 VCO's voltage isn't neatly 7.5 V( middle of supply voltage) which would happen at 90 degree phase difference between the two comparator inputs, but is sometimes below it, at about 5.5V; does this mean that I'm not exactly driving it at resonance? Or are there phase delays somewhere in the signal path? And does this mean that my phase is off by ((7.5V-5.5V)/15V)* 180 deg = 24 degrees?

The VCO takes the voltage required to achieve resonant frequency. If your supply is 15v and Fres is exactly at the midpoint of your PLL frequency range set by your R1 and R2 resistors, then 7.5v yields the right value. If your frequency is not the midpoint of your range you will need a different voltage value to get the right frequency. As the resonant point changes VCO will also change during the heating.

GeordieBoy

Mon Feb 01 2010, 10:02PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

> Richie, is there an optimal capacitance value or will any reasonable value work?

I really wouldn't worry about the dv/dt during the deadtime unless you are wanting to reduce EMI as much as possible. Companies that design commercial Induction Heaters for sale have to worry about this stuff.

> I have 1.0uf snubbers. Would 1.5uf be better?

Way way to big. Usually something between 220pF and 1nF is best to control the voltage slew-rate. It depends on the operating frequency, the amount of dead-time and the power level though. Lower operating frequency, more dead-time and high-power all make the optimal snubbing capacitance larger.

> ALso, during deadtime both mosfets are off, so how is the capacitor discharging?

Even though both MOSFETs are off during the dead-time, current continues to flow through the inductive part of the load. (Inductors act to prevent current from changing instantaneously.) It is this free-wheeling current that charges one device's capacitance and discharges the other in order to slew the inverter mid-point voltage from one rail to the other.

-Richie,

IamSmooth

Mon Feb 01 2010, 11:37PM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
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Posts: 1567

I see it now. I was looking at the wrong capacitor.

I am about to remake my HV DC power for an 8kw unit. My rectifier is 1000v/80A. That should be enough. I was going to have 50-100uf of capacitor for a voltage doubler. Is that reasonable to keep the PF close to unity? I currently have 1500uf.

Dinges

Tue Feb 02 2010, 11:42AM

Registered Member #2511 Joined: Mon Dec 07 2009, 02:46AM
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Richie wrote ...
I really wouldn't worry about the dv/dt during the deadtime unless you are wanting to reduce EMI as much as possible. Companies that design commercial Induction Heaters for sale have to worry about this stuff.

Richie, I think you are correct. Decided to scope both the gatedrive waveshape and the tankvoltage, and that was very telling:

Sine is the tank voltage, squarish-wave is the gate drive signal.

Notice that my gatedrive isn't entirely symmetric, due to an extra inverter (NAND gate) in a part of the gatedriver (see schematic here: http://picasaweb.google.com/motorconversion/Induction_heater#5433602260934568338); this extra NAND gate introduces 75ns delay (as measured), and accounts for the difference in rise and fall times of the gatedrive waveshape, of about 100ns (hard to estimate).

As can be seen in the top picture, the downslope of the gatedriver is a tad slower (by about 100ns) than the upslope; and notice that the noise on the tank voltage is larger in the case where the FETs switch faster.

So indeed, it looks like more deadtime leads to less RFI... but also to more switching losses in the FETs, as more time is spent dwelling in the linear region. I guess this is where the 'lossless' snubbers come in.

Oh, btw, I do have snubbers in the inverter, consisting of 2n2 capacitors in series with a 10R resistor; 3 snubbers in total, two over the switching transistors, and another one over the primary of the coupling transformer.

Peter.

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