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Finn Hammer

Tue May 26 2009, 10:11PM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

I am obsessed with finding a way to tweak out shoot trough in a pnp/npn totem pole.

The popular explanation is, that shoot trough exists for the range of voltage, where both fetÂ´s are turned on, which in a 30V systen can be as much as 24 volts, from 3V to 27V.

I had so focussed on the linear voltage aspect, that I forgot about the ever so important _time_, and this is why it didn't help to just stick in a zener in series with the gate.

The point is, that it takes *time* for the opto to rise from 0 to 30 volts, in this case 100nS. and then it takes another small 100nS for the upper fet to shut off. LetÂ´s give it another 100nS to settle in.

Then we have a need to, on a positive going edge, to delay the turn on of the low fet with 300nS, to insure that it does not start to conduct before the upper one has shut off.

Below is a schematic that I drew in a frenzy this morning to work, and pondered all day: will it work?

The point here is to spend 300nS filling up the capacitor to zener voltage, before charging the gate.
For 300nS, I would need 10nF and 30 ohms with a 18Volt zener, I ended up with 50 ohms.

Look at this small video, where I sweep the 2 resistors from 0 to 50 ohms, and watch the shoottrough drop from 6A to 100mA

Yellow trace shows the current spikes, green shows one of the fet gates, the other one omitted for clarity.

Looks a bit complicated, but set in smd parts, it should not take much space up on the board, really.

This design has only been tested on protoboard, and I assume it will be better on a proper pcb, which will follow in short order.

Instead of the zener, it would be really cool to use a Sidac, or Trisil, which would break down to 0Volts instead of clamp to zener voltage, in that case, the charge stored in capacitor would become instantly available as gate charge.
I am not shure, however, whether these devices are able to recompose between cycles at 30kHz.

So what, better leave good enough be for now.

Cheers, Finn Hammer

Firefox

Tue May 26 2009, 10:46PM

Registered Member #1389 Joined: Thu Mar 13 2008, 12:50AM
Location: Pittsburgh, PA
Posts: 346

Brilliant use of the RC time constant, Finn. :) Out of curiousity, do you know why you still have 100mA of shoot through, and is this acceptable for a bridge like this?

Finn Hammer

Wed May 27 2009, 04:51AM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

Firefox wrote ...

Brilliant use of the RC time constant, Finn. :) Out of curiousity, do you know why you still have 100mA of shoot through, and is this acceptable for a bridge like this?

Sean,

I am not sure there is any shoottrough left, actually. But the scope shows a bit of riffraff @100mA amplitude, and this could be diode reverse recovery, ground noise on a circuit with non-ideal grounding: no ground plane, or something else that I am unable to account for.
However, the good news is, that the bridge now delivers 10A into the Cm600 gate, with absolute smoothness, and it is this special smoothness that I am going for.
I cannot at the moment see why it does not deliver more, but looking into that.

There are a lot of RC time constants in this thread.

Cheers, Finn Hammer

Steve Conner

Wed May 27 2009, 09:35AM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

Hi Finn,

You were asking why it doesn't deliver more than 10 amps. The current could be limited by stray inductance, because inductance sets up a back EMF against changing current.

It could also be limited by gate capacitance: a capacitance can only draw current equal to C*dv/dt, so maybe you don't have enough dv/dt, if you slowed things down too much in your quest for special smoothness.

Another consideration is that since the gate is a capacitance, and the wiring to it is an inductance, you have a LC circuit. Even with the beefiest gate driver in the universe, with an infinite slew rate and infinite current capacity, the current you can deliver is limited by the surge impedance (sqrt(L/C)) of this circuit. However, if this was the limiting factor you would have a large voltage overshoot, up to 2x.

GeordieBoy

Wed May 27 2009, 11:15AM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

I agree with everything Steve said here. It pretty much sums up gate drive. I smile when I hear of people wanting to buy the latest gate-drive chip that can source more amps to MOSFET gates, and then they tell me they're going to use a Gate Drive Transformer in between. The leakage inductance of the GDT is enough to ensure that the drivier chip never gets anywhere near it's peak current sourcing or sinking ability. And to add insult to injury you usually have to introduce additional gate-damping resistance anyway to tame overshoot and ringing. This resistance further decreases the peak current in practical operation!

On the holy-grail quest to eliminate shoot-through it is worth considering that there are several things that can *appear* like shoot-through. Depending on how you actually examine the bridge circuit to check for shoot-through you can observe any of the following:

1. Shoot-through current down the bridge legs due to cross-conduction of the device channels. This is plain and simple overlap of the conduction periods of the two switching devices and is very bad! If you close one switch before the other one is opened, then the supply is shorted and lots of current will flow during that time.

2. Current surges down the bridge legs due to forced reverse recovery of each device's co-packaged free-wheel diode. Under certain circumstances each free-wheel diode will undergo a forced reverse-recovery event when the opposite switch turns on. This causes a current surge down the bridge leg that looks like shoot-through, and has all of the same detrimental effects. It just happens that the current path is through one switch and one diode instead of through two switches.

3. Current surges down the bridge leg to charge device output capacitances. This is most noticeable in high-frequency high-voltage bridge circuits. Under certain loading conditions the turning on of each switch causes a surge of current to suddenly charge the output capacitance of the opposite device to the supply rail voltage. Again this looks like conventional shoot-through and has the same detrimental effects. This time the current path is through one switch and one switch's device capacitance even though it is "open" or in its "blocking" state!

In a practical system shoot-through current can be comprised of one or two of the above components. Number 1 should be insignificant if the gate-drive signals do not overlap and sufficient deadtime is included to allow each device to fully turn off before the opposing device turns on. The behaviours described in number 2 and number 3 depend on the load presented to the bridge. The capacitive turn-on shoot-through described in number 3 is particularly noticeable when there is no load connected to a bridge being run at high-frequency and high voltage, or when the load appears capacitive. An indutive load and sufficient deadtime can ensure that devices turn on with zero voltage across them and there is no capacitive charging current spikes at turn-on.

Similiarly the behaviour described in number 2 above, is most noticeable with a heavy capacitive load where the load current leads the applied voltage. This causes forced reverse recovery of the free-wheel diodes with the accompanying current spike that sets everything in the circuit ringing! This is most likely the largest cause of losses in a DRSSTC where the switching transistions take place after the load current has changed direction, and where all reasonable precautions have been taken to eliminate simple cross-conduction.

-Richie,

Dr. Drone

Wed May 27 2009, 05:38PM

Registered Member #290 Joined: Mon Mar 06 2006, 08:24PM
Location:
Posts: 1673

GeordieBoy

Wed May 27 2009, 06:15PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

I'm guessing that maybe Finn is trying to switch that 4000 amp current in a more controlled way so that he doesn't generate 600 volt spikes across his IGBTs.

Without having to allow +100% voltage margin for switching spikes, he might then choose to increase the supply voltage to process more power and generate bigger sparks.

-Richie,

Finn Hammer

Wed May 27 2009, 07:38PM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

Steve, Richie

I think I can say with certainty that what is seen is "real shoot trough". Both devices are turned on, in a time and voltage range that corresponds with the current spike measured.
It also disappears when the counter measure is implemented.

I have been running it in Microsim today, and this has given me insight that I did not have before.

The voltage available on the gate of the output fet's is related to the zener voltage in a way I had not figured out.
This voltage starts to rise when the zener voltage is reached, and then follows the voltage across the capacitor in the R/C delay line, but offset by the zener voltage.

If I chose a zener voltage up close to Vcc, the charging curve has flattened out considerably, and therefore the gate voltage will rise slowly. This will lead to a slow turn on/off of the output fet, and then also low dv/dt, as Steve mentioned. This is the situation I think is seen now.

To acheive maximum output risetime, the zener voltage has to be chosen at the point where the slope of the R/C network is steepest. For the matematically inclined, this is probably easy to do, but I did it graphically:

It looks like this happens around 2/3 up, or around 20V.

Let me point out that I think 10A into the gate is about ideal: My reference of excellence is Fatboy, which with a 5.6ohm gate resistor presumably has a gate charging current of 6-8amps.
So when this gate driver does it _without_ gate resistor, and in a way where it swoshes past the miller plateou without hesitation, and without overshoot, much has been acheived.

Time will tell.

Cheers, Finn Hammer

Dr. Drone

Wed May 27 2009, 09:22PM

Registered Member #290 Joined: Mon Mar 06 2006, 08:24PM
Location:
Posts: 1673

GeordieBoy

Thu May 28 2009, 11:23AM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

I totally agree that allowing a voltage safety margin and running the devices under their voltage rating is a good idea for reliability. Perhaps a similar approach should be adopted for peak current rating of IGBTs in DRSSTCs too!

My overall opinion on this from many years in the power electronics industry is that the IGBT bricks people use for DRSSTCs simply weren't designed to switch thousands of amps at frequencies up to 100kHz. They were designed to switch a few hundred amps at little more than 20kHz because there's little motivation to go any higher in the drives industry. That is why the voltage spikes exist, because the devices were simply never designed for the kind of service that we put them to.

For these reasons I think that investigating any clever drive schemes or snubbers that help improve this situation is commendable. You have to use what you've got, be creative and push the boundaries.

It is possible to run devices very close to their ratings in SSTC applications, you just have to make sure you do everything right. It just happens to be easier to derate everything and consider what's the worst that could happen.

-Richie,

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