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Finn Hammer

Sun May 10 2009, 05:31PM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

All,
Project mooving forward, of course slower than wanted and predicted.
However, here is schematic of controller, only missing status led's:
Burden resistors are mounted on the terminals, so that they can be exchanged together with the current transformer.

And board layout:

This has been a satisfying job. In the course of drawing the schematic, I finally got the hang of using the supply symbols, which greatly simplifies the schematic.
The layout has separate grounds for analog and digital section, and 100nF bypass capacitors are surface mount cheramics on the back of the board.

Since I etch this board myself, and donÂ´t have trough plating facilities, certain ground connections are pulled over to a via to connect to gnd.

Cheers, Finn Hammer

Finn Hammer

Thu May 14 2009, 09:31PM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

Arrh! The joy of prototyping!

Knowing that to make the circuit work, a board has to be laid out, and produced. Early attention to chip power supply has to be taken care of.
To make a 40nS comparator spit perfect square waves, supply decoupling must be done as by the book!

I am the first to regret the shabby look of the etch, but (many good excuses...)It's the small surface mount 0.1ÂµF caps I want to show off, and of course the blue wire shouting GOOF out loud. But never mind, even those many Bourns trimpots are not cheap, it is for sure: another board has to come after this one:

So many hours used to find out: does the idea work?
All the signals check out. I did the gate drivers for 5V since they are going to drive optocouplers ultimately, but since I have already cut traces, I am going to rewire them for 15V and drive the gate transformer for the "dummy"-bridge.
I made some invalid assumptions on the interface from the overcurrent protector too, that have to be worked out.
I have vacation now, and it is agreed that I don't work on the project for a couple days, untill then, I can smile at the memory of that precision rectifyer doing itÂ´s task at 8Vin, and 31kHz:

Cheers, Finn Hammer

Dr. Drone

Sat May 16 2009, 02:41AM

Registered Member #290 Joined: Mon Mar 06 2006, 08:24PM
Location:
Posts: 1673

hvguy

Mon May 18 2009, 08:52AM

Registered Member #289 Joined: Mon Mar 06 2006, 10:45AM
Location: Conroe, TX
Posts: 154

Great job with this thread, Finn!

I built this exact circuit, LM311 and all (fast comps too), about three years ago. I spent more than a month working with it. I too had good results on the bench and was able to easily adjust the system for perfect switching... BUT it ultimately proved of little use as the change in delay for from ~20ApK to 800Apk in my final test system was just too great and resulted in a phase change much greater than was needed. I tried many different R/L values and different CT ratios, etc. but could not find an ideal situation. This circuit definitely works great with a fixed or lightly varied current source, but with the dynamic load of a DRSSTC it just didn't cut it. It did work well in an SSTC feedback loop though... Ultimately I could not justify using it as the efficiency/performance gains where just not there. Also, since a very high speed comp was necessary to achieve perfect switching it was HIGHLY susceptible to any noise. I always had to run a full AL enclosure with feedthru caps and fiber controls when the system was under full power (~1kw). It was like trying to build a GHz RF amp

That being said, I'm not trying to burst the bubble on this one and I hope you come up with something I missed as this would be a really helpful addition to the classic DRSSTC.

It's funny, I remember around Y2K when I started experimenting with feedback based SSTC's (I believe I was the first or second (Jan Wagner?) to incorporate a feedback loop into a TC system) I accidentally created this situation. It was so bad, in fact, that it lead to me giving up on the CT idea and sticking with voltage feedback (oops!). It was actually Richie who helped me with my first open-loop SSTC so I'm glad to see he's involved with this thread... Good luck!

Oh, BTW, props on the scope; I love my 2014, can't beat the CF card storage and it never skips a beat even when inundated with Kw's of RF.

Finn Hammer

Mon May 18 2009, 09:08AM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

Thanks, Aron

Your post sure ads to the excitement, but then, WTH, I actually started this idea based on a sample and hold circuit, which will not have any variation in delay due to different output from an inductor.
May have to pull that circuit into service in the end.

Cheers, Finn Hammer

Finn Hammer

Tue May 19 2009, 08:47PM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

All,

Back from Paris, first on the list was to find out, whether the circuit works, (it does so, thank you) and whether the inductive component of the feedback current transformer burden, causes the feedwack signal to advance with rising current.
This does not appear to be the case:

Look at the video linked below:
Green is voltage out of bridge,
Cyan os current in tank, measured with Pearson model 101, and
Magenta is feedback signal, as measured across burden inductor and resistor.
I vary the current in the bridge from 50A to 500A
The 2 Magenta cursor lines help to convince you, that there is hardly any advance in the feedback signal within a 1:10 variation of current.

So now that this taken care of, I'l design a real kiss gate driver centered around the IXDD414 chip, which, since it is delivering it's drive through a 5.6ohm resistor, has more than enough omph:
Swinging up from -10V to +20V the current won't exeed 6A, but the IXDD can source and sink 14A.

Cheers, Finn Hammer

Finn Hammer

Sat May 23 2009, 07:28PM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

All,

I admit to being a sucker for symmetry. So the gate driver for "Thumper" had to be designed with this in mind. I fried the 4 IXDD414 chips in short order, no good reason found, so the search for another gate driver started.
I want an optocoupler so that the gates get pulled all the way to -10V, even though there is deadtime. A gate transformer wonÂ´t do that.
The fast opto's I mentioned earlier demanded a low supply, 6V, and so I deemed them unsuitable for this project. I had a stick with 50 pcs. HCPL3120, and they look perfect for the job. The supply voltage is as high as 30V so it can straddle the gate driver supply, and swing the gates of the PNP - NPN totem pole output from rail to rail. Only thing to find was MOSfets with a 30V Gss rating. A prolonged datasheet search unearthed suitable candidates from Fairchild, both 30V gate voltage and around 15A current rating. FQP17P10 and FQP18N20
I am slowing the turn on of the NPN part, and slowing the turn off of the top PNP part with resistor/diode combinations, to avoid shootthrough.
The optocoupler needs 10mA to light the diode, but I am driving 110mA trough the supply cable, and shunting the 100mA. This way I divide the noise by 10, I hope?.
The propagation delay is 500nS, and this should not be a problem, after all, the current zero prediction scheme was developed with this kind of delays in mind. I may have to measure and select matched pairs for diagonal bricks.
It is the CM600 I intend to drive, but I have 1200A/1700V types in stock too =:-o

The schematic is here:

Getting more and more used to surface mount parts, the board layout looks like this:

I will etch a prototype tomorrow, and determine the values of the gate resistor/diode networks, even though this has to be done on IRF540/9530 since the fancy good ones from Fairchild are in the mail.

Comments, advice and even flames are welcome!

Cheers, Finn Hammer

Finn Hammer

Mon May 25 2009, 08:08PM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

Today, I have been looking at the gate driver, in particular why it is a good idea to keep cross conduction to a minimum in the totem pole output MosFets of the driver.

If you heep the schematic of last post in mind, I will show some scope shots of the cross conduction currents that happen unless the turn on and off of the output transistors are duly subdued.

In this case, I have chosen to mount 470 ohms gate resistors, and 1n5819 diodes, to tame the fet's.
This has caused the Cross Conduction to drop to:

On the falling edge of the gate signal:

A nice and calm one ampere for 50nS
If I short out the gate resistor, R6 in above schematic, this happens:

Cross conduction rises to 5 amps, and more important, ugly ringing is introduced.

Same thing on the rising edge, with 470 ohms in place:

And with R3 shorted:

It is the ringing that causes me the most concern.

Look at this rather benign gate voltage/current profile, with the resistors in place:

Then relish what the same situation looks like, if shoot trough in the gate driver exists:

This concludes my take on gate drivers: Keep them nice and clean, before attaching an IGBT.

Cheeers, Finn Hammer

One thing that bothers me: I cannot for the love of god yank more than 4 ampere into those gates, even though the gate resistor is 5 ohms. Go figure......

hvguy

Tue May 26 2009, 12:37AM

Registered Member #289 Joined: Mon Mar 06 2006, 10:45AM
Location: Conroe, TX
Posts: 154

That video looked very promising, Finn. What was the current sweep range (dI)?

I'm glad to see people working with different GD arrangements. It seems everyone was stuck on GDICs for the beginning years of SS work. I too have had unexpected, costly, and seemingly unexplainable failures with GDICs. I stopped using them in most designs. I found the IXYS parts, while quite possibly the best available, where much more susceptible to failure if their rail voltage was higher than their signal input voltage, even though the DS says that should be fine. Their ENA pin also seems very likely to cause a failure if it is noisy.

I am a big believer in GDTs though; you just can't beat galvanic isolation and 0 insertion delay. I usually drive them with either a full bridge of N-CH FETs driven by a tiny GDT and SOGDIC, or a half bridge of P/N-CH parts. Everything is ultra compact SMT, as close to the IGBT as possible.

I'm really looking forward to seeing this system make arcs. Thanks for a good thread...

Finn Hammer

Tue May 26 2009, 06:00AM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

hvguy wrote ...

That video looked very promising, Finn. What was the current sweep range (dI)?

snip

I'm really looking forward to seeing this system make arcs. Thanks for a good thread...

The video showed a current sweep from 50A to 500A.

About gate drive: I am having a very hard time justifying my initial desicion to use opto's and separate gate drivers, when it would be so much simpler to build a nice little semi-high voltage bridge, and drive a step down gate drive transformer.
It is no easy task to configure the totem pole output stage of the driver and get both zero shoot trough as well as high current output ability:
When I slow down the turn on enough to keep shoot trough low, the turn on is prolonged so that the ability to deliver current within the time frame of turning on of the IGBT is impaired.
I will try the old trick with zeners on the gate, which you may recall from the days of the beefy driver.

(didn'd help)

What I _really_ need is a tiny NTC resistor, which could delay the ramp up to miller plateau, then turn low resistance there, to allow fast full turn on.

Well, this is fun anyway, and perhaps I should just make that bridge/gate tranny and get on with it.

Thanks for -your- work. It was the work of pioneers like yourself that got me started.

Cheers, Finn Hammer

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