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Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
The extra cycle thing at the end only occurs if you are using a VCO, because the *first* cycle is not synced with the interrupter (like it would be in real operation). The only condition that can cause that in real operation is by setting the interrupter timing *just* on the edge, but it doesnt matter really, its a perfectly safe condition.
Dan, i cannot find these illegal states. Ive gone through every possible sequence of events with the flip flop, and all conditions are predictable. The only possible problem is if S! and R! (Clr! and Pre!) go high simultaneously, which is pretty much impossible with my circuit. The circuit works perfectly for me, ive never had a problem with it. If you can point out the illegal state, id appreciate it. This is the schematic im using:
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Shh Dan! Don't use the "M" word.
Metastability is what you get when the data input to the flip-flop changes exactly as the clock is changing state. The flip-flop can't decide whether to accept the new data or reject it and hold the old stuff. What happens is undefined. The probability of hitting it at exactly the "wrong" time is very small, but if you do hit the sore point, the output can stick for a relatively long time before it makes its mind up. I think Dan was saying that some flip-flops can lose the plot completely and put their Q and Q' outputs in the same state.
All SSTC drivers that use flip-flops will suffer from this problem, including my PLL design. I knew about metastability and the possibility of illegal states when I designed it, and put two flip-flops in a row to make the odds of it happening a good deal steeper.
One electronics text I know of uses Jean Buridan's paradox to illustrate this effect. A dog is placed midway between two identical bowls of dog food and it's supposed to starve to death because it can't decide which to eat first. My driver circuit eats both and takes a whiz on your trouser leg.
Registered Member #15
Joined: Thu Feb 02 2006, 01:11PM
Location:
Posts: 3068
One of the problem conditions is when the PRE and CLR are simultaneously LOW. This produces a state where both Q and Q' are HIGH. This occurs on each rising edge of your interruptor pulse. When the interruptor goes HIGH, the CLR input on the JK goes LOW at this same time, because of the RC delay, the PRE input on the JK remains low for about 15us putting the flip-flop into a metastable state during this time. When the flip-flop is in a metastable condition, the outputs are undetermined and will tend to oscillate between logic 0 and 1.
Of course, the condition usually removes itself when either PRE or CLR goes HIGH again, but for 15us you have a condition where both Q and Q' are undetermined and maybe oscillating between 0 and 1.
Of course, as you said, it may not be an issue with the application you are using. Typically, you can generally tolerate metastable states so long as the clock period is greater than the time it takes for a metastable state to resolve itself to a stable condition.
As you said, your circuit may work perfectly okay, but as i pointed out, the metastable condition does exist on every interruptor pulse.
Registered Member #89
Joined: Thu Feb 09 2006, 02:40PM
Location: Zadar, Croatia
Posts: 3145
It's all in the first post. With primary feedback oscillation collapsed after few cycles, but later I found it working good with 10K resistor in series with CT output.
I found no bugs multimetering the input stage (diodes, cap, resistor..), problem seems to be a bit deeper that that.
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My first DRSSTC
