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uDR/SSTC design - updated with full bridge testing and current monitoring..

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Nicko

Thu Jun 25 2009, 03:23PM

Registered Member #1334 Joined: Tue Feb 19 2008, 04:37PM
Location: Nr. London, UK
Posts: 615

I'm pretty new to SSTCs/DRSSTCs, but I'm in the middle of a new design & build with some fairly novel features... One part of which is a deceptively simple & reliable dead-time generator which I've not seen elsewhere. I hope this is useful for someone else...

The whole circuit is still in prototype but works well - In the spirit of sharing, I'll document the whole as I go...

System Diagram

]sstc_1_system_diagram.pdf[/file]

Dead Time
Basically, the feedback input is delayed by a fixed amount - taking into account the variable hysteresis of the schmitt there is a different RC time constant for the rise & fall of the feedback signal - with the values below, the input pulse edges are both delayed by about 85nS, and when recombined the result is a nice even 85nS shoulder for the UCC 3732x driver outputs. Deceptively simple & reliable - by taking advantage of the fact that one driver inverts the enable signal and the other doesn't, we can achieve a good result with far less complexity than is normal.

If anyone wants, I have the simulations in LTspice - though its easy to substitute 74HC(T) equivalents for the Tiny/LittleLogic gates I use.

NOTE: The inverting driver (UCC37321) is driven from the OR gate...

Full Bridge
The design is completely modular with both FB & HB versions for both FET & IGBT - easy to swap round for fun. The controller sits on top of this board and has been removed for the photo below.

Here is the prototype full bridge board (FET version) about to be tested...

Full Bridge Schematic

Controller
This can run in SSTC or DRSSTC mode and has built-in thermal management & protection together with optical link, remote control/information panel & dead-time control etc. etc.

Completed controller mounted on FET full bridge:

Test harness:

Test rig:

Synchroniser, optical link & feedback working:

Dead time generation working (needs minor adjustment):

Checking one side of the full bridge gate phasing:

Gate waveforms are in anti-phase and look ok:

Adjustable MMC (bleed resistors on underside):

New test rig running at 190kHz with fibre optic interrupter:

Primary current measured using Pearson CT 150 - 15V in making 30Vp-p:

http://4hv.org/e107_plugins/forum/forum_viewtopic.php?90019.post

LithiumLord

Thu Jun 25 2009, 04:55PM

Registered Member #1739 Joined: Fri Oct 03 2008, 10:05AM
Location: Moscow, Russia
Posts: 261

heh, kinda alike to what I use, the only difference is the usage of single delay and two different logic types for output. I prefer two separate delays and two AND gates as it utilizes one AND gate IC and some of hc14's gates you are not using completely anyway most likely - so, two ICs vs three ;) Also less parts, as you are no longer forced to use the diodes.

Nicko

Thu Jun 25 2009, 05:18PM

Registered Member #1334 Joined: Tue Feb 19 2008, 04:37PM
Location: Nr. London, UK
Posts: 615

LithiumLord wrote ...

...so, two ICs vs three ;) Also less parts, as you are no longer forced to use the diodes.

Well, you might save 1 component as you'll have an extra passive (capacitor) but you'll also be using more gates, and you'll note I'm using TinyLogic, which means the footprint is.... well... tiny ! (and no wasted gates).

Z28Fistergod

Thu Jun 25 2009, 07:38PM

Registered Member #2040 Joined: Fri Mar 20 2009, 10:13PM
Location: Fairfax VA
Posts: 180

That looks just like a circuit used to provide independent turn on and turn off waveforms at the gate of an IGBT or MOSFET. Finn hammer uses an almost identical circuit in his design too. If you came up with that on your own then that's good, although it's always a bummer to find out that one of your innovations is old news.

Also you have the problem of the intrinsic delay associated with your circuit. I don't want to sound too critical but schmitt triggers aren't supposed to be used in that way either, a comparator would be ideal.

Nicko

Thu Jun 25 2009, 07:52PM

Registered Member #1334 Joined: Tue Feb 19 2008, 04:37PM
Location: Nr. London, UK
Posts: 615

Z28Fistergod wrote ...

That looks just like a circuit used to provide independent turn on and turn off waveforms at the gate of an IGBT or MOSFET. Finn hammer uses an almost identical circuit in his design too. If you came up with that on your own then that's good, although it's always a bummer to find out that one of your innovations is old news.

I think you've missed the point - The trick with a schmitt input & the two diodes/resistors has probably been around for 20 or 30 years (or more) - it's a standard logic trick and nothing new in that whoever uses it . Just looked at what I think you are referring to (Prediktor?) and whilst Finn uses the same trick as part of his ZCS detection, it's not anything to do with dead time.

What I haven't seen used before (not in these parts anyway) is recombining the delayed pulse with the original using just two gates to generate the correct deadtimes. It's so simple...

Z28Fistergod

Thu Jun 25 2009, 08:52PM

Registered Member #2040 Joined: Fri Mar 20 2009, 10:13PM
Location: Fairfax VA
Posts: 180

Well no I didn't miss the point, this will probably sound bad but I didn't see what was so great about the AND gate and the OR gate combination, so I assumed you were talking about the diode resistor capacitor network.

I'd like to see the rest of you schematic because I think you may have overlooked something. It looks like the output of the OR gate will always be greater than 50% duty cycle and the output of the AND gate will always be less than 50% duty cycle. This is probably not good, and you might want to rethink your design.

Nicko

Thu Jun 25 2009, 09:22PM

Registered Member #1334 Joined: Tue Feb 19 2008, 04:37PM
Location: Nr. London, UK
Posts: 615

Z28Fistergod wrote ...

Well no I didn't miss the point, this will probably sound bad but I didn't see what was so great about the AND gate and the OR gate combination, so I assumed you were talking about the diode resistor capacitor network.

I'd like to see the rest of you schematic because I think you may have overlooked something. It looks like the output of the OR gate will always be greater than 50% duty cycle and the output of the AND gate will always be less than 50% duty cycle. This is probably not good, and you might want to rethink your design.

The design of the output is quite intentional - and, amusingly, quite subtle - The GDT drivers are the "standard" UCC 3732x pair (see original post) - one inverts its enable pin, the other does not - when driven by the pair of signals from the two gates, the dead time is generated -, i.e. one output is positive logic, the other negative which is why you thought that there was an error - it looks "wrong" at first sight, but isn't.

Run a brief simulation in LTspice or similar and you'll see it does actually work, counter-intuitive though it may appear...

HTH

Z28Fistergod

Thu Jun 25 2009, 09:32PM

Registered Member #2040 Joined: Fri Mar 20 2009, 10:13PM
Location: Fairfax VA
Posts: 180

Oops, your right. You must have the inverting driver on the OR gate.

Nicko

Thu Jun 25 2009, 09:43PM

Registered Member #1334 Joined: Tue Feb 19 2008, 04:37PM
Location: Nr. London, UK
Posts: 615

Z28Fistergod wrote ...

Oops, your right. You must have the inverting driver on the OR gate.

Exactly.

My point really with this very small offering is that simple can be quite cute - as you said, its just a couple of gates and a delay - the trick is combining that with the input to generate the correct drive for the UCCs - the absolute lack of complexity is exactly what makes it so neat (IMHO). Just replace the resistors with multi-turn pots and you have fully adjustable dead time.

When I looked a few months ago at how others were generating dead time, assuming they bothered at all, I was surprised at how complex they'd made it. A bit of thought, playing with LTspice & a breadboard, and a far simpler solution emerges... less often really is more...

Z28Fistergod

Thu Jun 25 2009, 09:48PM

Registered Member #2040 Joined: Fri Mar 20 2009, 10:13PM
Location: Fairfax VA
Posts: 180

I agree with less is more most of the time. What drove you to bother with the dead time in the first place?

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