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Registered Member #3704
Joined: Sun Feb 20 2011, 01:13PM
Location: Vermont, U.S.A.
Posts: 92
NOTE: After working more on this project, I have decided to build a DRSSTC, rather than a standard SSTC as I originally planned. Many of my earlier posts no longer apply.
Hi folks,
I joined some time ago but dropped off the map for a bit. Now I'm back for a little assistance.
I recently got around to starting my own DRSSTC design, though to be honest I have no idea what I'm doing--I'm learning as I go. I have drawn out a basic circuit utilizing the TC4420/9 MOSFET drivers (one non-inverting, and one inverting) and a full H-bridge to drive the primary. A 1:50 transformer on the secondary passes a feedback signal through some cleanup circuitry (two Schmitt-trigger inverters) back into the 4420/9.
I have little no doubt there is a fair amount that I missed, or that is calculated incorrectly, but I figured if anyone could look it over and critique it, it would be you folks.
The circuit is only in the design stage, so a lot of the part numbers (FETs, especially) are not the actual components I will be using. I only used them in the circuit to get the simulation to work, since PROTEUS did not have all of the components I planned to use. So I guess just consider them symbolically and don't pay much attention to the actual part numbers.
Any help would be greatly appreciated. As I said, this is entirely new to me and I am continuously trying to learn. Let me know if you would also like the Proteus design files for simulation.
Your high side fets are lacking a return current path for the gate drive signal. When the low side left fet is off there's no connection between the high side left Source and ground except through the primary and the low side right fet. Abandon the center tapped GDT and run a standard pentafiliar 1:1:1:1:1 GDT.
I'm not sure what you're doing with TR1 and TR2, but you left out the actual TC primary (unless one of those is meant to be coreless). Just use a single current transformer for feedback on the primary circuit, and don't ground any side of the primary circuit. What you have there looks more like you're trying to impedance match the inverter to the load, but that's only needed when running an inverter away from resonance, which you won't be doing.
Registered Member #3704
Joined: Sun Feb 20 2011, 01:13PM
Location: Vermont, U.S.A.
Posts: 92
Sigurthr wrote ...
Your high side fets are lacking a return current path for the gate drive signal. When the low side left fet is off there's no connection between the high side left Source and ground except through the primary and the low side right fet. Abandon the center tapped GDT and run a standard pentafiliar 1:1:1:1:1 GDT.
I'm not sure what you're doing with TR1 and TR2, but you left out the actual TC primary (unless one of those is meant to be coreless). Just use a single current transformer for feedback on the primary circuit, and don't ground any side of the primary circuit. What you have there looks more like you're trying to impedance match the inverter to the load, but that's only needed when running an inverter away from resonance, which you won't be doing.
Hi Sigurthr, thanks for the response.
I just realized I posted the wrong schematic. I've re-attached it, this time with the correct one.
TR1, as shown in the notes, is the primary/secondary. It should be coreless but I am not sure how to create coreless transformers for use in Proteus. I should have mentioned that in my original post. I am using a cored transformer just for the sake of simulation, and it does not reflect the actual circuit I will be using.
TR2 is the feedback transformer, which consists of 1 turn of the secondary and 50 turns going to the feedback cleanup circuitry.
I'm not sure what you're referring to when you say there's no return path for the gate drive signal. The GDT is grounded on the center tap, and the "bottom" of the H-bridge is also grounded. Was thinking that would serve as the return? When the left FET is off, then so is the low-side right FET, and the high-side right and low-side left FETs are on, feeding current through the Primary.
That's a good idea using the 1:1:1:1:1 though. I am assuming that is one winding for the TC4420/9, and one for each FET, am I correct?
Yep, in pentafiliar one is for the primary, and four secondaries - one for each fet. This balances inductances and interwinding capacitances evenly.
The Gate-Source current of Q1 has to flow through the primary and then through DS junction of Q3 in order to return to the grounded center tap of the GDT. The same goes for Q4 and Q2. The problem is that this means that Q1 cannot turn on until Q3 has turned on, and the time Q3 spends in the linear state causes Q1 to spend an even longer time in the linear state. Not to mention the additional impedances presented to the gate drive current from having to flow through the primary which will likely greatly distort the gate signals. The result is instead of switching on as Q1/Q3 then Q2/Q4 you get Q3 then Q1 then Q2 then Q4. This greatly magnifies losses and presents a huge cross conduction hazard.
Also, you need a DC blocking capacitor on the primary of the GDT or else the GDT will appear as a short to the gate drive chips, blowing them up.
My instinct says that grounding the center tap of the GDT also causes you to present the full voltage differential between the positive rail of the Bus and ground to the Gate-Source junction, which will surely destroy the fets. It is late and I'm getting a bit fuzzy doing the simulation of this running in my head so take this last part with a grain of salt, but it doesn't look viable to me.
Registered Member #4074
Joined: Mon Aug 29 2011, 06:58AM
Location: Australia
Posts: 335
Sigurthr wrote ...
Yep, in pentafiliar one is for the primary, and four secondaries - one for each fet. This balances inductances and interwinding capacitances evenly.
My instinct says that grounding the center tap of the GDT also causes you to present the full voltage differential between the positive rail of the Bus and ground to the Gate-Source junction, which will surely destroy the fets. It is late and I'm getting a bit fuzzy doing the simulation of this running in my head so take this last part with a grain of salt, but it doesn't look viable to me.
I believe this is correct. The voltage you need to apply to the gates is relative to the SOURCE of the MOSFET. If the inverter is running off rectified 230V then the source of the high side transistors will be way over a hundred volts away from ground - so your grounded GDT will cause the gates to be annihilated instantly (and a lot of fault current will flow through the GDT and dead transistors - flames and booms). With isolated GDT windings, you connect the "bottom" of the coil (remembering correct phasing) directly to the source pin of the transistor that winding is driving. Then the "top" of that coil connects to the gate through the appropriate-sized gate resistor. Now the gate voltage is relative to the source of the FET - even if it's floating at several hundred volts the gate will only see the +/- 12-20 volt (whatever you choose) produced by the GDT. It's a good idea to use wire with decent insulation in your GDT, since it will be experiencing a couple of hundred volts. Its also a good idea to use "back to back" zeners across the gate and source pins to protect the gates from any unwanted spikes.
At least, that's what I'm seeing right now, if I'm wrong hopefully someone will point it out :)
Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
Hello, I'm afraid you still don't understand basics of electronics (there are really a lot of flaws in your circuit), I don't mean this in an offensive way but I think you should really follow a tried design for your first coil, like the Mini SSTC by Steve Ward.
Registered Member #3704
Joined: Sun Feb 20 2011, 01:13PM
Location: Vermont, U.S.A.
Posts: 92
Hi Everyone,
This is a lot of great feedback, thank you very much! It looks like I'll definitely have to re-think a lot of my circuit, so I'll keep this in mind when redrawing it.
I'll post back when I have something more.
@Dr. Dark Current-- The point of this project is not simply to build a SSTC. It's to learn how to design one. The design process is the most important part, so simply taking someone else's design really doesn't interest me. And for the record, I understand the basics of electronics, but SSTCs have a lot going on at once and my brain often can't keep up :p
Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
I think the best way to get started is to build a proven design and then learn from it. I'd say this is the quickiest way to learn and then you'll be able to design a much better circuit.
But anyway: -Pulling the gate drivers' inputs low or high during OFF-time is wrong, you must make sure that both drivers outputs are LOW or both HIGH during the OFF-time. Use the ENABLE pins of G-drivers or NAND gates.
-The GDT connection is horribly wrong. Just look at any other SSTC design, they all use similar connection of GDT secondaries.
-The GDT should have a 1:1 turns ratio. Wind it by insulated wires twisted together (eg. wires from an UTP cable) to form a "stranded wire". This way you'll get the lowest leakage inductance.
-Connect a 1-10uF ceramic/film cap in series with GDT primary to block DC voltage.
-Remove the resistor on CT output and replace it with a ~10nF capacitor to block DC voltage. The zener diode has a too high capacitance and it will increase your loop delay; use two 1N4148 diodes to clamp the CT output to the zener diode (to decrease capacitances).
-Gate driver decoupling caps are not drawn but I suppose you'll use them.
-The bridge is missing its decoupling capacitor as well.
-If the circuit is to be used as an DRSSTC, a primary current feedback is a much better option than secondary base current feedback.
Registered Member #3704
Joined: Sun Feb 20 2011, 01:13PM
Location: Vermont, U.S.A.
Posts: 92
Excellent comments, Dr. Dark Current, thank you. This is why I came here--for replies like yours!
Dr. Dark Current wrote ...
I think the best way to get started is to build a proven design and then learn from it. I'd say this is the quickiest way to learn and then you'll be able to design a much better circuit.
The other issue I didn't mention was that I am limited for parts, and do not have much cash to spend on this project. The idea was to design a SSTC (still not sure if I want to go for a DRSSTC or not) that your average hobbyist with little cash can build. I realize it may not be this simple, but that was the hope, anyway.
Dr. Dark Current wrote ... But anyway: -Pulling the gate drivers' inputs low or high during OFF-time is wrong, you must make sure that both drivers outputs are LOW or both HIGH during the OFF-time. Use the ENABLE pins of G-drivers or NAND gates.
Okay, that makes sense. I am used to needing pull-up/pull-down resistors and did not realize they would not work in this case. The TC4420/9 do not have enable pins. Also, since one driver is inverting and one non-inverting, I thought they were always supposed to be opposite of each other, thus creating the +/- 5V oscillation on the primary of the GDT. So you're saying they should both be on or both be off when the interrupter is low? I guess I don't really see the logic in this.
Dr. Dark Current wrote ... -The GDT connection is horribly wrong. Just look at any other SSTC design, they all use similar connection of GDT secondaries.
Yes, that has been pointed out to me and quite honestly I'm not sure what I was thinking. I don't know why I used a grounded center tap, and I can see how it's horribly wrong =P
I have opted for the 1:1:1:1:1 transformer, as was suggested earlier. Unfortunately Proteus does not seem to have a model for this, so may have to start drawing it by hand and forgetting about the simulations. The first and third secondaries of the GDT will be in phase with the input, and the second and fourth secondaries will be out of phase. The first will be connected to the gate and source of the left high-side MOSFET, the second is connected to the right high-side MOSFET, the third will be connected to the right low-side MOSFET, and the fourth will be connected to the left low-side MOSFET. Does this sound right? I will be sketching it up eventually, and I will see about posting it again.
Dr. Dark Current wrote ... -The GDT should have a 1:1 turns ratio. Wind it by insulated wires twisted together (eg. wires from an UTP cable) to form a "stranded wire". This way you'll get the lowest leakage inductance.
Okay, good. That's what I was planning on, so it's good to know I had *something* right (except for the turns ratio)!
Dr. Dark Current wrote ... -Connect a 1-10uF ceramic/film cap in series with GDT primary to block DC voltage.
Noted and added!
Dr. Dark Current wrote ... -Remove the resistor on CT output and replace it with a ~10nF capacitor to block DC voltage. The zener diode has a too high capacitance and it will increase your loop delay; use two 1N4148 diodes to clamp the CT output to the zener diode (to decrease capacitances).
I originally had a 100nF capacitor connected to the CT output, I'm not sure what happened to it. I must have deleted it when I moved things around and forgot to put it back in. Would 100nF have been okay, or should it be closer to the 10nF you recommended? Someone also suggested I simply get rid of the zener and use a shottkey, or even simpler, two 4148s to clamp the output to the 5V rail. What are your thoughts on this?
Dr. Dark Current wrote ... -Gate driver decoupling caps are not drawn but I suppose you'll use them.
Good point, and they have been noted.
Dr. Dark Current wrote ... -The bridge is missing its decoupling capacitor as well.
Noted.
Dr. Dark Current wrote ... -If the circuit is to be used as an DRSSTC, a primary current feedback is a much better option than secondary base current feedback.
I had not thought of that until someone suggested it earlier. Now, correct me if I'm wrong, but a primary feedback signal is produced by putting a transformer in series with the primary, am I correct? And then I will need to rectify it and process it so that it passes a square wave back into the drivers?
Thanks again everyone for the great information. It certainly helps!
Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
wrote ...
So you're saying they should both be on or both be off when the interrupter is low? I guess I don't really see the logic in this.
When the interrupter is disabled, there should be no voltage on the GDT primary. As you pointed out, the drivers by itself are always at opposite logic levels when the inputs are connected, so in this configuration they are unable to turn off the GDT. Also, you did want to power the gate drivers from 5 volts? NO, use 12 or 15 volts.
wrote ...
Would 100nF have been okay, or should it be closer to the 10nF you recommended? Someone also suggested I simply get rid of the zener and use a shottkey, or even simpler, two 4148s to clamp the output to the 5V rail. What are your thoughts on this?
I would use 10 nF but I guess it doesn't matter much. The 10 nF one will quicker block the DC voltage. In this application, you can clamp the CT output to the 5V rail by two 1N4148 diodes. The current here is small. If the current would be larger, you would need to make sure the voltage of the 5V rail does not increase because of the additional rectified "supply current"; in this case it's best to clamp the input to the zener diode instead of the 5V supply.
wrote ...
Now, correct me if I'm wrong, but a primary feedback signal is produced by putting a transformer in series with the primary, am I correct? And then I will need to rectify it and process it so that it passes a square wave back into the drivers?
You use a CT in a similar configuration like your secondary base current sense, just pass the primary wire through it instead of the secondary ground. The current on the CT output will be increased of course, so the clamping circuit and nearby components would need to be modified. There are different ways of dealing with this.
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First SSTC design - Need some critique
